Semiconductor memory device and semiconductor system including the same
AssigneeHynix Semiconductor Inc.
InventorSung-Mook Kim
Life of this patent
Estimating the term…
Abstract
A semiconductor memory device includes a memory block configured to store a data inputted/outputted through a data transfer line, a data output block configured to output the data loaded on the data transfer line in response to a source clock, wherein the data output block is controlled to be coupled with the data transfer line in response to a write operation signal, a write operation signal generation block configured to generate the write operation signal in response to an operation selection signal and a reference clock lagging behind the source clock by a set time, and a data input block configured to load the data on the data transfer line in response to the write operation signal.
Claims23
A semiconductor memory device, comprising:
- a memory block configured to store a data transferred through a data transfer line;
- a data output block configured to output the data loaded on the data transfer line in response to a source clock, wherein the data output block is controlled to be coupled with the data transfer line in response to a write operation signal;
- a write operation signal generation block configured to generate the write operation signal in response to an operation selection signal and a reference clock lagging behind the source clock by a set time;
- and
- a data input block configured to load the data on the data transfer line in response to the write operation signal,
- wherein the data output block comprises:
- a data output enable pulse generator configured to generate a data output enable pulse that is activated for a predetermined time whenever the source clock pulses;
- a data sense amplifier configured to sense-amplify the data loaded on the data transfer line for a period that the data output enable pulse is activated, latch a sense-amplified data, and output a latched data;
- and
- an access controller configured to control the data sense amplifier to be coupled with the data transfer line in response to the write operation signal.
A semiconductor memory device, comprising:
- a plurality of memory blocks configured to store data transferred through a plurality of data transfer lines, respectively;
- a plurality of data output blocks configured to output the data loaded on the data transfer lines in response to a source clock, wherein the data output blocks are controlled to be coupled with the data transfer lines in response to a plurality of write operation signals;
- a write operation signal generation block configured to generate the write operation signals in response to a plurality of operation selection signals that respectively correspond to the memory blocks and a reference clock lagging behind the source clock by a set time;
- and
- a plurality of data input blocks configured to load the data on the data transfer lines in response to the write operation signals, respectively.
A method for operating a semiconductor memory device inputting/outputting a data through a data transfer line, comprising:
- latching a data loaded on the data transfer line in response to a source clock and outputting a latched data to outside;
- loading an external data on the data transfer line in response to a reference clock lagging behind the source clock by a set time, when an operation selection signal is activated;
- and
- receiving the source clock and the reference clock through different clock input pads.
A semiconductor system, comprising:
- a controller configured to control an operation selection signal to be activated or inactivated;
- and
- a semiconductor memory device configured to perform a data read and write operation or a data read operation within one cycle of a source clock based on whether the operation selection signal is activated or inactivated,
- wherein the semiconductor memory device, when the operation selection signal is activated, latches a data stored therein and outputs a latched data for a set time whenever the source clock pulses, and receives and stores a data transferred from the controller therein after the output of the latched data, and
- the semiconductor memory device, when the operation selection signal is inactivated, outputs the data stored therein to the controller whenever the source clock pulses.
Dependencies are inferred from the claim text.