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US 8,643,162 B2Granted
Pads and pin-outs in three dimensional integrated circuits
OwnerRaminda Udaya Maduraweinventor
Life of this patent
Estimating the term…
Abstract
A three dimensional semiconductor device, comprising: a substrate including a plurality of circuits; a plurality of pads, each pad coupled to a said circuit; and a memory array positioned above or below the substrate coupled to a said circuit to program the memory array.
Claims20
A semiconductor device, comprising:
- a first layer including a configuration circuit;
- a second layer including a plurality of circuits;
- and
- a third layer including a plurality of pads, wherein the configuration circuit is configured to be dependent on at least one of the plurality of circuits to access information from an external source through the plurality of pads, wherein the configuration circuit is operable to use the information to configure at least one of the plurality of circuits, and wherein the first layer, the second layer, and the third layer form a stack.
1 more element
A method, comprising:
- forming a stack comprising a first layer including a configuration circuit, a second layer including a plurality of circuits, and a third layer including a plurality of pads;
- and
- coupling a portion of the plurality of circuits to the plurality of pads, wherein the configuration circuit is configured to be dependent on at least one of the plurality of circuits to access information from an external source through the pads, and wherein the configuration circuit is operable to use the information to configure at least one of the plurality of circuits.
A semiconductor device, comprising:
- a substrate including a plurality of circuits;
- a first layer including a configuration circuit;
- and
- a second layer including a plurality of pads, wherein the configuration circuit is configured to be dependent on at least one of the plurality of circuits to access information from an external source through the pads, wherein the configuration circuit is operable to use the information to configure at least one of the plurality of circuits, and wherein the substrate, the first layer, and the second layer form a stack.
1 more element
Dependencies are inferred from the claim text.