Chip-on-Wafer structures and methods for forming the same

A device comprising:

• a wafer comprising:
• a plurality of chips comprising a plurality of through-substrate vias penetrating through a semiconductor substrate of the wafer;
• and
• a plurality of scribe lines separating the plurality of chips from each other;
• a plurality of dies underlying and bonded to a front side of the wafer;
• a first polymer region comprising:
• first portions in the plurality of scribe lines, penetrating through the wafer, and contacting sidewalls of the semiconductor substrate;
• and
• second portions at a same level as, and encircling, the plurality of dies;
• a plurality of conductive features on a back side of the semiconductor substrate and electrically coupled to the plurality of through-substrate vias;
• and
• a second polymer layer comprising:
• first portions covering edge portions of the plurality conductive features;
• and
• second portions over and aligned to the first portions of the first polymer region.

A device comprising:

• a package component comprising a substrate, wherein the substrate comprises a front surface, and a back surface over the front surface;
• a through-via penetrating through the substrate;
• a die underlying and bonded to a front side of the package component;
• a polymer encircling, and in contact with, sidewalls of the substrate and sidewalls of the die, wherein the polymer comprises a bottom surface level with a surface of the die, and a top surface level with or higher than the back surface of the substrate;
• and
• an insulation layer over the substrate, wherein the insulation layer comprises a bottom surface contacting the back surface of the substrate and a top surface of the polymer, and wherein the through-via penetrates through the insulation layer.