Wafer dicing using femtosecond-based laser and plasma etch
AssigneeApplied Materials, Inc.
InventorsWei-Sheng Lei, Brad Eaton, Madhava Rao Yalamanchili, Saravjeet Singh, Ajay Kumar, James M. Holden
Life of this patent
Estimating the term…
Abstract
Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer. The mask is composed of a layer covering and protecting the integrated circuits. The mask is patterned with a femtosecond-based laser scribing process to provide a patterned mask with gaps. The patterning exposes regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then etched through the gaps in the patterned mask to singulate the integrated circuits.
Claims13
A method of dicing a semiconductor wafer comprising a plurality of integrated circuits, the method comprising:
- forming a mask above the semiconductor wafer, the mask comprising a layer covering and protecting the integrated circuits;
- patterning the mask with a femtosecond-based laser scribing process to provide a laser-scribed mask with scribe lines each having a width, the scribe lines exposing regions of the semiconductor wafer between the integrated circuits;
- and
- plasma etching trenches into the semiconductor wafer to singulate the integrated circuits, the trenches each having the width.
A method of dicing a semiconductor wafer comprising a plurality of integrated circuits, the method comprising:
- forming a polymer mask layer above a silicon substrate, the polymer mask layer covering and protecting integrated circuits disposed on the silicon substrate, the integrated circuits comprising a layer of silicon dioxide disposed above a layer of low K material and a layer of copper;
- patterning the polymer mask layer, the layer of silicon dioxide, the layer of low K material, and the layer of copper with a femtosecond-based laser scribing process to provide a laser scribed polymer mask with scribe lines each having a width, the scribe lines exposing regions of the silicon substrate between the integrated circuits;
- and
- plasma etching trenches into the silicon substrate to singulate the integrated circuits, the trenches each having the width.
Dependencies are inferred from the claim text.