US 8,633,732 B2Granted

Circuits for soft logical functions

AssigneeMitsubishi Electric Research Laboratories, Inc.

InventorsDavid Reynolds, Benjamin Vigoda

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Abstract

A circuit implementing a soft logical processing network includes an interconnection of analog processing elements, which can include soft logic gates, for instance soft Equals gates and soft XOR gates. In some examples, each of the soft logic gates include multiple circuit parts, with each part including an input configured to accept a voltage signal representation of a soft logical quantity, and a conversion section configured to use the accepted voltage representation to form a corresponding current signal. The current signals are combined to form a signal representation of the output of the gate. In an application of soft logic gates, a memory includes a group of electrical storage elements, each electrical storage elements carrying a respective storage values; a group of conversion elements, each conversion element being coupled to a respective electrical storage element for selectively converting the corresponding storage value to a current signal; and a current combination element for combining the current signals to form an output signal.

Claims19

Dependent claims

A circuit implementing a soft logical processing network comprising an interconnection of analog processing elements including soft logic gates, the soft logic gates comprising one or more soft Equals gates, each soft Equals gate comprising:

a plurality of circuit parts, each part including
an input configured to accept a voltage signal representation of a soft logical quantity, and
a conversion section configured to convert the accepted voltage representation to a corresponding current signal representation of the soft logical quantity;
a signal combination part coupled to the conversion sections of the plurality of circuit parts and configured to form a signal representation of the sum of the soft logical quantities represented in the current signals;
an output for providing the signal formed by the signal combination part;
wherein in each circuit part, the input is configured to receive a differential voltage signal representation of the soft logical quantity on a plurality of signal lines and each signal line is coupled to a corresponding transistor in the conversion section configured to operate in an above threshold mode, the transistors providing a differential current that is substantially proportional to the soft logical quantity represented in the received differential voltage signal.

3 more elements

a plurality of circuit parts, each part including
an input configured to accept a voltage signal representation of a soft logical quantity, and
a conversion section configured to use the accepted voltage representation form a current signal that depends on the soft logical quantity;
wherein in at least a first circuit part of the plurality of circuit parts, the conversion section is configured to convert the accepted voltage representation to provide a corresponding current signal representation of the soft logical quantity;
and
wherein in at least a second circuit part of the plurality of circuit parts, the conversion section is configured to combine the accepted voltage representation and the current signal representation provided by another of the circuit parts to provide a current signal representation;
wherein the soft logic gate further comprises a signal combination part coupled to the conversion section of one or more of the circuit parts to form a current signal representation of an output of the soft logic gate;
and
wherein at least one of the soft logic gates is at least one of configured and configurable to implement a gate selected from the group consisting of a soft AND gate, a soft OR gate, and a soft NAND gate.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 12/716,148Filed 2 Mar 2010 · us provisional application
Priority: 2 Mar 2009
Published: US 2010/0306164 A12 Dec 2010
Granted: 21 Jan 2014
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

G11C 27/026
Using a capacitive memory element: associated with an amplifier
H03K 19/09432
Using field-effect transistors: with coupled sources or source coupled logic
H03K 19/09436
With coupled sources or source coupled logic: source coupled field-effect logic [SCFL]
G06N 7/01
Computing arrangements based on specific mathematical models: probabilistic graphical models, e.g. probabilistic networks

Family

Application61/156,794Us provisional application · filed 2 Mar 2009
Application61/156,721Us provisional application · filed 2 Mar 2009
Application61/156,792Us provisional application · filed 2 Mar 2009
Application61/156,735Us provisional application · filed 2 Mar 2009
Application61/293,999Us provisional application · filed 11 Jan 2010
US 2010/0306164 A1Pre-grant publication · published 2 Dec 2010
US 8,633,732 B2This patent

From the US filing history. Foreign family members aren’t listed.