Method and circuit for testing accuracy of delay circuitry
AssigneeXilinx, Inc.
InventorAndrew W. Lai
Life of this patent
Estimating the term…
Abstract
In one embodiment a circuit for testing delays is provided. A test signal generator circuit toggles a plurality of output signals 1 through N in sequential order, separating the toggles by a delay period. Each output signal is coupled to an input of a respective one of a plurality of delay circuits. A phase detector circuit is coupled to the delay circuits and is configured to determine the order in which signals output from delay circuits X−1, X, and X+1 are toggled for each delay circuit X. In response to the output signals being toggled in the order X−1 followed by X followed by X+1, the phase comparator circuit is configured to output a first signal indicating correct operation. Otherwise, the phase comparator circuit is configured to output a second signal indicating incorrect operation.
Claims17
A circuit for testing a plurality of delay circuits in an integrated circuit (IC), comprising:
- a test signal generator circuit configured to generate a plurality of output signals 1 through N, and in response to an input signal, toggle the plurality of output signals in sequential order from 1 to N with a delay period between the toggle of each output signal X and the toggle output signal X+1 of the N output signals, each output signal being coupled to an input of a respective one of the plurality of delay circuits;
- and
- a phase detector circuit coupled to outputs of the plurality of delay circuits, the phase detector circuit, for an output signal of each delay circuit X of delay circuits 2 through N−1, configured to:
- output a first signal indicating delay circuit X is operational in response to the output signals of delay circuits X−1, X, and X+1 being toggled in the order X-1 followed by X followed by X+1;
- and
- output a second signal indicating delay circuit X is not operational in response to the output signals of delay circuits X−1, X, and X+1 being toggled in an order other than X−1 followed by X followed by X+1;
- wherein for each delay circuit X of the plurality of delay circuits, the phase detector includes a flip flop X having a clock input coupled to receive the output signal of delay circuit X, a clock enable input coupled to receive the output signal of delay circuit X−1, a synchronous reset input coupled to receive the output signal of delay circuit X+1, a data input, and a data output that provides a respective output signal of the phase detector circuit.
A method for testing delay circuits in an integrated circuit (IC), comprising:
- toggling input signals to a plurality of N delay circuits in sequential order from 1 to N, with a delay period between the toggle of the input signal to each delay circuit X and the toggle of the input signal to delay circuit X+1 of the plurality of delay circuits;
- and
- for each delay circuit X of delay circuits 2 through N−1, performing operations including:
- determining an order in which output signals of delay circuits X−1, X, and X+1 toggle;
- wherein determining the order in which the output signals of delay circuits X−1, X, and X+1 toggle includes:
- inputting the output signal of delay circuit X−1 to a clock enable input of a flip-flop;
- inputting the output signal of delay circuit X to a clock input of the flip-flop;
- and
- inputting the output signal of delay circuit X+1 to a synchronous reset input of the flip-flop;
- in response to the output signals of delay circuits X−1, X, and X+1 being toggled in the order X−1 followed by X followed by X+1, storing a first data value indicating delay circuit X is operational;
- and
- in response to the output signals of delay circuits X−1, X, and X+1 being toggled in an order other than X−1 followed by X followed by X+1, storing a second data value indicating delay circuit X is not operational.
An article of manufacture, comprising:
- a non-transitory storage medium configured with configuration data that when loaded onto a programmable integrated circuit cause a set of programmable circuits to operate as built-in self test (BIST) circuitry, the BIST circuitry configured to perform the operations including:
- toggling input signals to a plurality of N delay circuits in sequential order from 1 to N, with a delay period between the toggle of the input signal to each delay circuit X and the toggle of the input signal to delay circuit X+1 of the plurality of delay circuits;
- and
- for each delay circuit X of delay circuits 2 through N−1, performing operations including:
- determining an order in which output signals of delay circuits X−1, X, and X+1 toggle;
- wherein determining the order in which the output signals of delay circuits X−1, X, and X+1 toggle includes:
- inputting the output signal of delay circuit X−1 to a clock enable input of a flip-flop;
- inputting the output signal of delay circuit X to a clock input of the flip-flop;
- and
- inputting the output signal of delay circuit X+1 to a synchronous reset input of the flip-flop;
- in response to the output signals of delay circuits X−1, X, and X+1 being toggled in the order X−1 followed by X followed by X+1, outputting a first data value indicating delay circuit X is operational;
- and
- in response to the output signals of delay circuits X−1, X, and X+1 being toggled in an order other than X−1 followed by X followed by X+1, outputting a second data value indicating delay circuit X is not operational.
Dependencies are inferred from the claim text.