Electrically programmable and erasable memory device and method of fabrication thereof

A method of forming a memory device comprising:

• providing a substrate;
• providing a tunneling layer over the substrate;
• providing a floating gate over the tunneling layer, the floating gate comprising a plurality of electrons;
• providing a dielectric over the floating gate, wherein providing the dielectric over the floating gate comprises:
• depositing a first insulating layer over the floating gate, the first insulating layer being formed by depositing a silicon dioxide layer over the floating gate,
• depositing a second insulating layer comprising a silicon oxynitride layer over the first insulating layer,
• depositing a third insulating layer comprising a silicon nitride layer over the second insulating layer;
• providing a control gate over the dielectric;
• and
• providing a source and a drain in the substrate,
• wherein the source and the drain are in contact with opposite sides of a bottom surface of the tunneling layer,
• wherein, the memory device is electrically erased by applying a positive voltage to the control gate and the drain while holding the source at ground and allowing the substrate to float, the positive voltage being of sufficient magnitude to eliminate a barrier presented by the second insulating layer, and to reduce barriers presented by the first and third insulating layers,
• wherein the positive voltage provides a plurality of holes in the control gate with sufficient energy to overcome a valence energy level of the first and third insulating layers, and to cause the plurality of holes to travel through the first, second, and third insulating layers,
• further wherein, a conductive energy level of the second insulating layer is higher than a conductive energy level of the third insulating layer.