Device with power control feature involving backup power reservoir circuit
AssigneeSeagate Technology LLC
InventorDarren Edward Johnston
Life of this patent
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Abstract
Power-backup capabilities are provided by implementing a variety of different methods, systems and devices. According to one such implementation, an energy storage device such as a capacitive storage circuit is powered relative to the powering of one or more additional circuits from a common power supply to limit the draw upon the power supply. Certain applications involve delaying or otherwise modifying the powering of the capacitive storage circuit, which may involve an initial startup of the capacitive storage circuit.
Claims22
A data storage device that stores data in response to data accesses under the control of a memory control circuit, the data storage device comprising:
- a primary memory circuit configured and arranged to maintain data integrity in the absence of operating power;
- a solid-state caching memory circuit mapped to the primary memory circuit and configured and arranged to provide the memory control circuit with access to a set of data representing a cached portion of memory that is mapped to the primary memory circuit, the caching memory circuit including a controller configured to control backup functions of the caching memory circuit in response to a power interruption;
- a backup power-reservoir circuit that includes a capacitor coupled to receive a charge from a power supply, and that is configured to hold a charge to supply backup power for powering backup functions of the caching memory circuit;
- and
- a power supply control circuit configured and arranged to control, in response to a determined type and number of memory circuits in the data storage device, offset charging of the backup power-reservoir circuit relative to powering of another memory circuit to limit a current load upon the power supply according to a threshold current.
A data storage device that stores data in response to data accesses under the control of a memory control circuit, the data storage device comprising:
- a power supply;
- a primary memory circuit configured and arranged to maintain data integrity in the absence of operating power;
- a solid-state caching memory circuit mapped to the primary memory circuit and configured and arranged to provide the memory control circuit with access to a set of data representing a cached portion of memory that is mapped to the primary memory circuit, the caching memory circuit including a controller configured to control backup functions of the caching memory circuit in response to a power interruption;
- a backup power-reservoir circuit that includes a capacitor coupled to receive a charge from the power supply, and that is configured to hold a charge to supply backup power for powering backup functions of the caching memory circuit;
- and
- a power supply control circuit configured and arranged to
- in response to a number and type of memory circuits in the data storage device, select a power startup algorithm from a set algorithms respectively for starting a combination of memory circuits including the backup power-reservoir circuit and at least another memory circuit, at least one of the algorithms for starting up a memory circuit of a different type than the backup power-reservoir circuit, and
- execute the selected algorithm to control offset charging of the backup power-reservoir circuit relative to powering of another memory circuit to limit a current load upon the power supply according to a threshold current.
A method of controlling a data storage device that stores data in response to data accesses under the control of a memory control circuit, the data storage device including power supply, a primary memory circuit that maintains data integrity in the absence of operating power, a solid-state caching memory circuit that is mapped to the primary memory circuit and provides the memory control circuit with access to a set of data representing a cached portion of memory that is mapped to the primary memory circuit, a controller configured to control backup functions of the caching memory circuit in response to a power interruption, and a backup power-reservoir circuit that includes a capacitor coupled to receive a charge from the power supply, and that holds a charge to supply backup power for powering backup functions of the caching memory circuit, the method comprising:
- controlling, in response to a determined type and number of memory circuits in the data storage device, offset charging of the backup power-reservoir circuit relative to powering of another memory circuit to limit a current load upon the power supply according to a threshold current.
A method of controlling a memory device that stores data in response to data accesses under the control of a memory control circuit, the memory device including a power supply, a primary memory circuit that maintains data integrity in the absence of operating power, a solid-state caching memory circuit that is mapped to the primary memory circuit and provides the memory control circuit with access to a set of data representing a cached portion of memory that is mapped to the primary memory circuit, and a backup power-reservoir circuit that includes a capacitor coupled to receive a charge from the power supply, and that holds a charge to supply backup power for powering backup functions of the caching memory circuit, the method comprising:
- in response to a number and type of memory circuits in the memory device, selecting a power startup algorithm from a set algorithms respectively for starting a combination of memory circuits including the backup power-reservoir circuit and at least another memory circuit, at least one of the algorithms for starting up a memory circuit of a different type than the backup power-reservoir circuit, and
- executing the selected algorithm to control offset charging of the backup power-reservoir circuit relative to powering of another memory circuit to limit a current load upon the power supply according to a threshold current.
Dependencies are inferred from the claim text.