Circuit arrangement and receiver including the circuit arrangement

A circuit arrangement, comprising:

• a first input terminal and a second input terminal;
• a first transistor and a second transistor, each of the first transistor and the second transistor having a first controlled terminal, a second controlled terminal and a control terminal, the first controlled terminal of the first transistor being coupled to the first controlled terminal of the second transistor, the control terminal of the first transistor being coupled to the first input terminal, the control terminal of the second transistor being coupled to the second input terminal, and the second controlled terminal of the first transistor being coupled to the second controlled terminal of the second transistor;
• a third transistor and a fourth transistor, each of the third transistor and the fourth transistor having a first controlled terminal, a second controlled terminal and a control terminal, the first controlled terminal of the third transistor being coupled to the first controlled terminal of the fourth transistor, the control terminal of the third transistor being coupled to the first input terminal, the control terminal of the fourth transistor being coupled to the second input terminal, and the second controlled terminal of the third transistor being coupled to the second controlled terminal of the fourth transistor;
• an input matching circuit coupled to the first input terminal, the second input terminal, the first transistor, the second transistor, the third transistor and the fourth transistor;
• a first resistive element coupled between the control terminal of the first transistor and the second controlled terminal of the first transistor;
• a second resistive element coupled between the control terminal of the second transistor and the second controlled terminal of the second transistor;
• a third resistive element coupled between the control terminal of the third transistor and the second controlled terminal of the third transistor;
• a fourth resistive element coupled between the control terminal of the fourth transistor and the second controlled terminal of the fourth transistor;
• a first output terminal coupled to the second controlled terminal of the first transistor and the second controlled terminal of the second transistor;
• and
• a second output terminal coupled to the second controlled terminal of the third transistor and the second controlled terminal of the fourth transistor;
• wherein the input matching circuit comprises a first inductor, a second inductor, a third inductor, a first capacitor, a second capacitor, a third capacitor and a fourth capacitor;
• wherein the first inductor comprises a first terminal coupled to the first input terminal, and a second terminal coupled to the control terminal of the first transistor and the control terminal of the third transistor;
• wherein the second inductor comprises a first terminal coupled to the first controlled terminal of the first transistor, the first controlled terminal of the second transistor, the first controlled terminal of the third transistor and the first controlled terminal of the fourth transistor;
• wherein the third inductor comprises a first terminal coupled to the control terminal of the second transistor and the control terminal of the fourth transistor, and a second terminal coupled to the second input terminal;
• wherein the first capacitor is coupled between the control terminal of the first transistor and the first controlled terminal of the first transistor;
• wherein the second capacitor is coupled between the control terminal of the second transistor and the first controlled terminal of the second transistor;
• wherein the third capacitor is coupled between the control terminal of the third transistor and the first controlled terminal of the third transistor;
• and
• wherein the fourth capacitor is coupled between the control terminal of the fourth transistor and the first controlled terminal of the fourth transistor.