Semiconductor storage device including variable resistive elements

A semiconductor storage device comprising:

• a memory cell array including a plurality of first lines, a plurality of second lines crossing the first lines, and memory cells arranged at intersections between the first lines and the second lines and each including a variable resistive element;
• and
• a control circuit which controls resistance values of the variable resistive elements in such a way that a cell voltage is applied to the memory cells arranged at an intersection between a selected one of the first lines and a first-selected one of the second lines and at an intersection between the selected first line and a second-selected one of the second lines by applying a first voltage to the selected first line, by applying a second voltage to the first-selected second line, and by applying a third voltage to the second-selected second line, wherein
• the control circuit applies a voltage gradually raised or lowered from a first initial voltage as the first voltage to the selected first line, applies a pulsing voltage as the second voltage to the first-selected second line, and applies a pulsing voltage as the third voltage to the second-selected second line, and
• the second voltage includes a voltage pulse which is raised from a second initial voltage which the memory cell is a non-selected state of the memory cell to a voltage which the memory cell is a selected state, is kept at the raised voltage to thereby cause a cell current to flow into the memory cell, and is lowered to the second initial voltage when the cell current that increases while the voltage of the memory cell is rising along with a change in the first voltage reaches a compliance current, and
• the third voltage includes a voltage pulse which is raised from the second initial voltage which the memory cell is the non-selected state to the voltage which the memory cell is the selected state of the memory cell, is kept at the raised voltage to thereby cause a cell current to flow into the memory cell, and is lowered to the second initial voltage when the cell current that increases while the voltage of the memory cell is rising with the change in the first voltage reaches a compliance current.