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US 8,621,597 B1Granted
Apparatus and method for automatic self-erasing of programmable logic devices
AssigneeXilinx, Inc.
InventorJesse H. Jenkins, IV
Life of this patent
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Abstract
Programmable logic devices (PLDs), programmable logic arrays (PLAs), complex programmable logic devices (CPLDs), and field programmable gate arrays (FPGAs), (collectively referred to as “PLDs”) can include circuitry for performing automatic erasing or “zeroization” of security information including data and programming. Such circuitry detects the occurrence of a possible security event, selects and/or forms one or more appropriate erase commands, and causes the command(s) to be executed against PLD memory. The circuitry prevents security information from being compromised under certain situations.
Claims29
A programmable device comprising:
- a security event detection circuit receiving a signal from at least one of an external pin and a logic block, the signal indicating possible occurrence of an event that can compromise circuit security;
- an erase controller coupled to the security event detection circuit, wherein the erase controller forms at least one configuration memory erase command and transmits the at least one configuration memory erase command to a programming interface responsive to a detected security event;
- wherein the programming interface circuit is coupled to the erase controller, wherein the programming interface circuit erases at least a portion of a configuration memory that programs the programmable device responsive to receiving, and according to, the at least one configuration memory erase command;
- and
- a status information memory, coupled to the erase controller that is distinct from the configuration memory, storing status information comprising a record of memory addresses of the configuration memory subject to erasure as specified by each configuration memory erase command formed by the erase controller and transmitted to the programming interface, wherein the record of memory addresses is retained subsequent to erasure of the at least a portion of the configuration memory;
- an erase information memory coupled to the erase controller, wherein the erase information memory is preloaded with a list of memory addresses to be erased responsive to the security event and the erase information memory further stores priority information indicating an order in which the addresses in the list of memory address are to be erased by the erase controller according to criticality of information stored in the configuration.
3 more elements
A method performed within a programmable device comprising:
- detecting an occurrence of a security event;
- responsive to detecting the security event, preparing at least one configuration memory erase command specifying a portion of a configuration memory;
- transmitting the at least one configuration memory erase command to a programming interface;
- responsive to receiving the at least one configuration memory erase command, erasing the specified portion the configuration memory that programs the programmable device according to the at least one configuration memory erase command;
- storing, within a status information memory that is distinct from the configuration memory, status information comprising a record of memory addresses of the configuration memory subject to erasure as specified by each configuration memory erase command prepared and transmitted to the programming interface, wherein the record of memory addresses is retained subsequent to erasure of the at least a portion of the configuration memory;
- and
- storing erase information in a memory, the erase information including a list of configuration memory addresses to be erased and a priority order in which the addresses in the list are to be erased according to criticality of information stored in the configuration memory.
4 more elements
A programmable device comprising
- a means for detecting an occurrence of a security event;
- a means for preparing at least one configuration memory erase command specifying a portion of a configuration memory responsive to detecting the security event, wherein the means for preparing the at least one configuration memory erase command is operable responsive to the security event;
- a means for transmitting the at least one configuration memory erase command to a programming interface;
- a means for erasing the specified portion of the configuration memory that programs the programmable device responsive to receiving, and according to, the at least one configuration memory erase command;
- a means for storing status information comprising a record of memory addresses of the configuration memory subject to erasure as specified by each configuration memory erase command prepared and transmitted to the programming interface, wherein the record of memory addresses is retained subsequent to erasure of the at least a portion of the configuration memory;
- and
- means for storing erase information in a memory, the erase information including a list of configuration memory addresses to be erased and a priority order in which the addresses in the list are to be erased according to criticality of information stored in the configuration.
4 more elements
Dependencies are inferred from the claim text.