US 8,621,487 B2 · Virtual processor methods and apparatus with unified event notification and consumer-producer memory operations

Abstract

The invention provides, in one aspect, a virtual processor that includes one or more virtual processing units. These virtual processing units execute on one or more processors, and each virtual processing unit executes one or more processes or threads (collectively, “threads”). While the threads may be constrained to executing throughout their respective lifetimes on the same virtual processing units, they need not be. The invention provides, in other aspects, virtual and/or digital data processors with improved dataflow-based synchronization. A process or thread (collectively, again, “thread”) executing within such processor can execute a memory instruction (e.g., and “Empty” or other memory-consumer instruction) that permits the thread to wait on the availability of data generated, e.g., by another thread and to transparently wake up when that other thread makes the data available (e.g., by execution of a “Fill” or other memory-producer instruction).

Claims29

Dependent claims

An embedded processor, comprising

A. a plurality of processing units, each of which execute one or more processes or threads (which one or more processes or threads are collectively referred to as “threads”) and one or more of which execute a plurality of threads,
B. one or more execution units that are shared by, and in communication coupling with, the plurality of processing units, the execution units executing instructions from the threads,
C. an event delivery mechanism that delivers events to respective threads with which those events are associated, wherein a said event is any of (i) a hardware interrupt generated other than by the processing unit that is executing the thread to which that hardware interrupt is delivered, (ii) a software interrupt generated other than by the thread to which that software interrupt is delivered, wherein the event delivery mechanism:
i. is in communication coupling with the plurality of processing units, and
ii. delivers each such event to the respective thread without execution of instructions by said processing units, and
D. wherein the thread to which an event is delivered processes that event without execution of instructions outside that thread.

3 more elements

An embedded processor system, comprising

A. a plurality of embedded processors,
B. a plurality of virtual processing units executing on the plurality of embedded processors, each virtual processing unit executing one or more processes or threads (which one or more processes or threads are collectively referred to as “threads”) such that one or more embedded processors has plural threads executing thereon, and each thread being any of constrained or not constrained to execute on a same virtual processing unit and/or a same processor during a life of that thread,
C. one or more execution units that are shared by, and in communication coupling with, the plurality of virtual processing units, the execution units executing instructions from the threads, the execution units including any of integer, floating, branch, compare and memory execution units,
D. an event delivery mechanism that delivers events to respective threads with which those events are associated, wherein a said event is any of (i) a hardware interrupt generated other than by the processing unit that is executing the thread to which that hardware interrupt is delivered, (ii) a software interrupt generated other than by the thread to which that software interrupt is delivered, wherein the event delivery mechanism:
i. is in communication coupling with the plurality of virtual processing units, and
ii. delivers each such event to the respective thread without execution of instructions by said virtual processing units,
E. wherein the thread to which an event is delivered processes that event without execution of instructions outside that thread.

4 more elements

A method of embedded processing, comprising the steps of

A. executing a plurality of virtual processing units on a plurality of embedded processors,
B. executing one or more processes or threads (which one or more processes or threads are collectively referred to as “threads”) on each of a plurality of virtual processing units such that one or more embedded processors has plural threads executing thereon, each thread being any of constrained or not constrained to execute on a same virtual processing unit and/or a same embedded processor during a life of that thread,
C. executing instructions from the threads in one or more execution units that are shared by the plurality of virtual processing units, the execution units including any of integer, floating, branch, compare and memory execution units, and
D. delivering events to respective threads with which those events are associated without execution of instructions by said virtual processing units, wherein a said event is any of (i) loading of cache memory following a cache miss by the thread to which that event is delivered, (ii) filling of a memory location by a thread, other than the thread to which that notification is delivered, in response to a memory instruction issued by the thread to which that notification is delivered,
E. wherein step (D) is effected without executing instructions by said processing units, and
F. processing the event by the thread to which the event is delivered without execution of instructions outside that thread.

3 more elements

Dependencies are inferred from the claim text.

Virtual processor methods and apparatus with unified event notification and consumer-producer memory operations

Life of this patent

Virtual processor methods and apparatus with unified event notification and consumer-producer memory operations

Life of this patent

Abstract

Claims29