Multi core optimizations on a binary using static and run time analysis

A computer storage hardware storing computer executable instructions which when executed by a processor perform a method comprising:

• identifying a first thread and a second thread of a plurality of threads of an application, the first thread comprising a first operation, the second thread comprising a second operation;
• determining a potential conflict between the first operation and the second operation, the determining a potential conflict comprising comparing a frequency of execution of a first edge corresponding to the first operation to a frequency of execution of a second edge corresponding to the second operation;
• and
• at least one of creating or modifying a layout based at least in part on the potential conflict.

A system comprising:

• one or more processing units;
• and
• memory comprising instructions that when executed by at least one of the one or more processing units perform a method comprising:
• identifying a first thread and a second thread of a plurality of threads of an application;
• determining a potential conflict between a first operation of the first thread and a second operation of the second thread, the determining a potential conflict comprising determining that the first operation and the second operation access a first memory location within a threshold time window, at least one of the first operation or the second operation comprising a write operation;
• comparing a frequency of execution of a first edge comprised in the first thread to a frequency of execution of a second edge comprised in the second thread;
• and
• at least one of creating or modifying a layout based at least in part on at least one of the potential conflict or the comparison.