Automated top down process to minimize test configurations for multi-feature products
AssigneeIntel Corporation
InventorSatwant Kaur
Life of this patent
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Abstract
Systems and methods of conducting interoperability assessments provide for generating a feature interoperability matrix based on feature data and interoperability data, wherein the feature data defines a plurality of features of a product and the interoperability data indicates levels of interoperability of the plurality of features. A validation set can be generated based on the feature interoperability matrix, wherein the validation set includes a plurality of feature combinations. A subfeature interoperability matrix can be used to convert the validation set into a test plan for the product, wherein the test plan minimizes test configurations for the product.
Claims31
A method comprising utilizing a processor causing:
- generating a feature interoperability matrix based on feature data and interoperability data, wherein the feature data defines a plurality of features of a product and the interoperability data indicates levels of interoperability of the plurality of features;
- generating a validation set based on the feature interoperability matrix, the validation set including a plurality of feature combinations;
- identifying a plurality of feature pairs based on the validation set and the feature interoperability matrix;
- receiving a subfeature interoperability matrix for each of the plurality of feature pairs;
- and
- generating a test plan for the product based on the subfeature interoperability matrix and dependency data for the plurality of features.
A computer readable storage medium comprising a set of instructions which, if executed by a processor, cause a computer to:
- identify a feature pair of a product, a first set of subfeatures for the feature pair, and a second set of subfeatures for the feature pair;
- receive a subfeature interoperability matrix, wherein the subfeature interoperability matrix is to indicate a level of interoperability of the first and second sets of subfeatures;
- and
- generate a test plan to include a list of platform exercises based on the subfeature interoperability matrix and a plurality of exercises associated with the first and second sets of subfeatures.
A system comprising:
- a processor;
- and
- a memory including a set of stored instructions which, if executed by the processor, cause the system to,
- identify a feature pair of a product, a first set of subfeatures for the feature pair, and a second set of subfeatures for the feature pair,
- receive a subfeature interoperability matrix, wherein the subfeature interoperability matrix is to indicate a level of interoperability of the first and second sets of subfeatures, and
- generate a test plan to include a list of platform exercises based on the subfeature interoperability matrix and a plurality of exercises associated with the first and second sets of subfeatures.
A method comprising utilizing a processor causing:
- identifying a feature combination for a product;
- expanding the feature combination to include an additional feature only if the additional feature is interoperable with all features in the feature combination and the additional feature is new to the feature combination;
- and
- adding the feature combination and the expanded feature combination to a validation set for the product.
Dependencies are inferred from the claim text.