Micro-regions for auto place and route optimization

A computer-implemented method comprising:

• partitioning by a computer a first floorplan of a first version of a circuit design into a plurality of micro-regions including at least a first micro-region, wherein a size of the first micro-region is determined based at least in part on a number of changes likely to be located in an area that corresponds to the first micro-region;
• and
• generating a micro-region specification including information corresponding to at least the first micro-region;
• and
• utilizing the micro-region specification, wherein the micro-region specification is usable as a constraint on placement of logic elements during generation of the second floorplan for the second version of the circuit design, and wherein the micro-region specification requires each logic element in the first micro-region of the first floorplan to be located within an area corresponding to the first micro-region in the second floorplan.

A computing system comprising:

• a placement unit, wherein the placement unit is configured to generate a first floorplan of a first version of a circuit design and a second floorplan of a second version of the circuit design;
• and
• a partitioning unit, wherein the partitioning unit is configured to:
• partition the first floorplan into a plurality of regions including at least a first micro-region, wherein a size of the first micro-region is based at least in part on a number of changes between the first version of the circuit design and a second version of the circuit design which are located in an area corresponding to the first micro-region;
• and
• generate a micro-region specification including information corresponding to at least the first micro-region, wherein the micro-region specification is usable as a constraint on placement of logic elements during generation of the second floorplan.

A non-transitory computer readable storage medium comprising program instructions, wherein when executed the program instructions are operable to:

• determine one or more changes between a first version of a circuit design and a second version of the circuit design, the first version having a corresponding first floorplan;
• determine an area of the first floorplan to which the one or more changes are likely to correspond;
• partition the first floorplan of the first version of the circuit design into a plurality of micro-regions including at least a first micro-region, wherein a size of the first micro-region is based at least in part on a number of said one or more changes;
• generate a micro-region specification including information corresponding to at least the first micro-region, wherein the micro-region specification is usable as a constraint on placement of logic elements during generation of a second floorplan for the second version of the circuit design.