Back to results
US 8,621,410 B2Granted
Multiprocessor computer system and method having at least one processor with a dynamically reconfigurable instruction set
AssigneeFTL Systems, Inc.
InventorJohn C. Willis
Life of this patent
Estimating the term…
Abstract
An innovative realization of computer hardware, software and firmware comprising a multiprocessor system wherein at least one processor can be configured to have a fixed instruction set and one or more processors can be statically or dynamically configured to implement a plurality of processor states in a plurality of technologies. The processor states may be instructions sets for the processors. The technologies may include programmable logic arrays.
Claims13
A method of computer processing comprising:
- supplying source code to a computer having at least one processor having a first instruction set and at least one dynamically reconfigurable logic array;
- analyzing the source code to identify one or more processor states;
- binding the one or more processor states to one or more technology types and subtypes;
- synthesizing logic to reconfigure the at least one dynamically reconfigurable logic array to execute the processor states;
- reconfiguring the at least one dynamically reconfigurable logic array to a specific set of cell designs and routing options to implement the one or more technology types and subtypes;
- executing the one or more processor states on the at least one processor and on the at least one reconfigured logic array;
- wherein the one or more processor states executing on the reconfigured logic array are different than the one or more processor states executing on the at least one processing processor having the first instruction set.
4 more elements
A method of computer processing comprising:
- supplying source code to a computer having at least one processor having a fixed first instruction set and at least one dynamically reconfigurable logic array, the at least one dynamically reconfigurable logic array not implemented on a same integrated circuit as the at least one processor;
- analyzing the source code to identify one or more processor states;
- binding the one or more processor states to one or more technology types and subtypes not embedded in the source code;
- synthesizing logic to reconfigure the at least one dynamically reconfigurable logic array to execute the processor states;
- reconfiguring the at least one dynamically reconfigurable logic array to a specific set of cell designs and routing options to implement addition of one or technology types and subtypes;
- executing the one or more processor states on the at least one processor and on the at least one reconfigured logic array;
- wherein the one or more processor states executing on the reconfigured logic array are different than the one or more processor states executing on the at least one processor having the fixed first instruction set;
- wherein executing the one or more processor states on the reconfigured logic array does not require determining on an instruction-by-instruction basis whether the reconfigured logic array is configured with one or more technology types to execute the one or more processor states on the reconfigured logic array;
- and
- wherein the at least one processor is not designed to natively offload said one or more processor states executing on the at least one processor to the reconfigured logic array.
7 more elements
Dependencies are inferred from the claim text.