US 8,621,408 B2 · Progressive circuit evaluation for circuit optimization

Abstract

Systems and techniques for optimizing a circuit design are described. Some embodiments reduce the number of gates in the library (e.g., by dynamically pruning the library) which are considered for optimization. Some embodiments create a linear delay model, and use the linear delay model instead of a non-linear delay model to substantially reduce the amount of computation required to check whether or not a particular replacement gate improves one or more metrics of the circuit design. Some embodiments determine an order for processing the gates in the library or for processing input pins of a gate to facilitate early rejection of a candidate gate in the library of gates. In some embodiments, the evaluation of the impact of a candidate gate transformation is done progressively and level-by-level only up to the point where the gate transformation degrades one or more metrics.

Claims18

Dependent claims

A method for optimizing a circuit design, the method comprising:

evaluating, by computer, a first candidate gate from a library of gates as a replacement for a gate that is being optimized, wherein said evaluating involves computing one or more timing metrics based on the first candidate gate;
responsive to rejecting the first candidate gate based on said evaluating, storing one or more parameter values of the first candidate gate;
determining whether a second candidate gate from the library of gates degrades the one or more timing metrics by comparing one or more corresponding parameter values of the second candidate gate with the one or more stored parameter values, wherein said determining does not involve computing the one or more timing metrics based on the second candidate gate;
and
rejecting the second candidate gate based on said determining.

2 more elements

A computer system, comprising:

a processor;
and
a storage medium storing instructions that, when executed by the processor, cause the computer system to perform a method for optimizing a circuit design, the method comprising:
evaluating a first candidate gate from a library of gates as a replacement for a gate that is being optimized, wherein said evaluating involves computing one or more timing metrics based on the first candidate gate;
responsive to rejecting the first candidate gate based on said evaluating, storing one or more parameter values of the first candidate gate;
determining whether a second candidate gate from the library of gates degrades the one or more timing metrics by comparing one or more corresponding parameter values of the second candidate gate with the one or more stored parameter values, wherein said determining does not involve computing the one or more timing metrics based on the second candidate gate;
and
rejecting the second candidate gate based on said determining.

5 more elements

Dependencies are inferred from the claim text.

Progressive circuit evaluation for circuit optimization

Life of this patent

Progressive circuit evaluation for circuit optimization

Life of this patent

Abstract

Claims18