Apparatus and method for supporting circuit design, and semiconductor integrated circuit
AssigneeFujitsu Semiconductor Limited
InventorTsuyoshi Sakata
Life of this patent
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Abstract
In a circuit design support apparatus, a selection unit selects a delay circuit model from among two or more delay circuit models with wire load based on different values of physical parameters relating to wiring, on the basis of a difference value in a physical parameter between a first path and a second path, the first path being from a branch point of a clock signal line for supplying a clock signal to a register model of a semiconductor integrated circuit model to be designed up to a clock signal input terminal of the register model, the second path being from the branch point up to a data signal input terminal of the register model. An arrangement unit arranges the selected delay circuit model on a data signal line connected to the data signal input terminal.
Claims11
A circuit design support apparatus comprising:
- a selection unit to select a delay circuit from among two or more delay circuits with different wire load values, on the basis of a difference value in a physical parameter between a first path and a second path;
- and
- an arrangement unit to arrange the selected delay circuit on the first path or the second path, wherein:
- the first path is a path that leads to a clock signal input terminal of a first resister from a reference position of a clock signal line;
- and
- the second path includes a path leading to a clock signal input terminal of a second resister from the reference position of the clock signal line, and a path leading to a data signal input terminal of the first register from a data signal output terminal of the second register.
A circuit design support method comprising:
- selecting, by a processor, a delay circuit from among two or more delay circuits with different wire load values, on the basis of a difference value in a physical parameter between a first path and a second path;
- and
- arranging, by the processor, the selected delay circuit on the first path or the second path, wherein:
- the first path is a path that leads to a clock signal input terminal of a first resister from a reference position of a clock signal line;
- and
- the second path includes a path leading to a clock signal input terminal of a second resister from the reference position of the clock signal line, and a path leading to a data signal input terminal of the first register from a data signal output terminal of the second register.
A semiconductor integrated circuit comprising:
- a first register;
- a second register;
- and
- a delay circuit which has wire load that compensates for a difference value in a physical parameter between a first path and a second path, wherein:
- the first path is a path that leads to a clock signal input terminal of the first resister from a reference position of a clock signal line;
- and
- the second path includes a path leading to a clock signal input terminal of the second resister from the reference position of the clock signal line, and a path leading to a data signal input terminal of the first register from a data signal output terminal of the second register.
Dependencies are inferred from the claim text.