System and methods for converting planar design to FinFET design
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsCheok-Kei Lei, Yi-Tang Lin, Hsiao-Hui Chen, Yu-Ning Chang, Shu-Yu Chen, Chien-Wen Chen, Chih-Sheng Chang, Clement Hsingjen Wann
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Abstract
A method for generating a layout for a device having FinFETs from a first layout for a device having planar transistors is disclosed. The planar layout is analyzed and corresponding FinFET structures are generated.
Claims20
A method of generating integrated circuit (IC) designs comprising a FinFET structure layout, the method performed by a layout generating machine having a processor component executing instructions prior to manufacturing, said method comprising:
- receiving a planar structure layout for an IC design, the planar structure layout including a plurality of planar active areas;
- generating a plurality of FinFET active areas, wherein each FinFET active area corresponds to one planar active area of the plurality of planar active areas;
- defining a plurality of FinFET cells, wherein each FinFET cell includes one or more of the FinFET active areas;
- determining whether each of the plurality of FinFET cells is symmetrical;
- and
- for each symmetrical FinFET cells, generating mandrels in the FinFET cell to create an internally symmetrical FinFET active area or more than one symmetrical FinFET active areas each of the more than one symmetrical FinFET active areas having a same number and location of mandrels.
A method of generating integrated circuit (IC) designs comprising a FinFET structure layout, the method performed by a layout generating machine having a processor component executing instructions prior to manufacturing, said method comprising:
- receiving a planar structure layout for an IC design, the planar structure layout including a plurality of planar active areas;
- generating a plurality of FinFET active areas corresponding to the plurality of planar active areas;
- defining a plurality of FinFET cells, wherein each FinFET cell includes one or more FinFET boundaries including one or more of the plurality of FinFET active areas;
- determining whether each of the plurality of FinFET cells includes symmetrical FinFET boundaries;
- and
- generating mandrels in FinFET cells corresponding to the symmetrical FinFET boundaries to create an internally symmetrical FinFET boundary or more than one FinFET boundary with each of the more than one FinFET boundary having a same number and location of mandrels.
A method of generating integrated circuit (IC) designs comprising a FinFET structure layout, the method performed by a layout generating machine having a processor component executing instructions prior to manufacturing, said method comprising:
- receiving a planar structure layout for an IC design, the planar structure layout including a plurality of planar cells, each cell comprising one or more planar active areas;
- determining whether each of the plurality of planar cells is symmetrical;
- generating a plurality of FinFET active areas corresponding to the plurality of planar active areas;
- defining a plurality of FinFET cells corresponding to the plurality of planar cells;
- for each symmetrical planar cell, generating symmetrical mandrels in each corresponding FinFET cell.
Dependencies are inferred from the claim text.