Timing closure methodology including placement with initial delay values

An automated method for designing an integrated circuit layout with a computer, comprising:

• in a logic design phase:
• selecting cells from a cell library to implement a circuit path;
• determining initial delay values and corresponding gain for the selected cells prior to assignment of wireloads based on an initial placement of the circuit path;
• determining an adjusted initial delay value and corresponding gain for at least one of the selected cells prior to the assignment of wire loads based on the initial placement of the circuit path, by performing at least one of:
• compressing the initial delay value of at least one of the selected cells to meet delay constraints for the circuit path, and
• stretching the initial delay value of at least one of the selected cells to reduce slack in the circuit path;
• and
• in a physical design phase:
• performing the initial placement of the selected cells for the circuit path, and the assignment of wire loads to the selected cells based on the initial placement;
• adjusting size or area of one or more of the selected cells during or after the initial placement to maintain the initial delay value or the adjusted initial delay value for the corresponding selected cells;
• routing the selected cells for the circuit path;
• and further including
• determining net weight values for the selected cells, the net weight values representing sensitivity of total area of a circuit design to load on the corresponding cell, and prior to placement of the circuit path, determining whether to insert a buffer on the output of a given cell in the selected cells using the net weight value of the given cell, and inserting a buffer in the circuit path when there is available slack in the circuit path.