Detecting memory corruption
AssigneeJuniper Networks, Inc.
InventorsSamuel Jacob, Vijay Paul
Life of this patent
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Abstract
A device identifies, based on a program code instruction, an attempted write access operation to a fenced memory slab, where the fenced memory slab includes an alternating sequence of data buffers and guard buffers. The device assigns read-only protection to the fenced slab and invokes, based on the attempted write access operation, a page fault operation. When a faulting address of the attempted write operation is not an address for one of the multiple data buffers, the device performs a panic routine. When the faulting address of the attempted write operation is an address for one of the multiple data buffers, the device removes the read-only protection for the fenced slab and performs a single step processing routine for the program code instruction.
Claims20
A method performed by a network device, the method comprising:
- configuring, by a processor of the network device, a memory block as a fenced slab that includes multiple data buffers and multiple guard buffers;
- assigning, by the processor, a read-only protection to the fenced slab;
- identifying, by the processor, an attempted write access operation, based on a program code instruction, to one of the multiple data buffers or multiple guard buffers;
- recording, by the processor and in a control register, a faulting address for the attempted write access operation;
- invoking, by the processor and based on the identifying the attempted write access operation, a page fault operation;
- retrieving, by the processor and from the control register, the faulting address;
- determining, by the processor, whether the faulting address is associated with the fenced slab;
- determining, by the processor and when the faulting address is associated with the fenced slab, whether the faulting address is an address for one of the multiple data buffers;
- performing, by the processor and when the faulting address is not an address for one of the multiple data buffers, a panic routine;
- removing, by the processor and when the faulting address is an address for one of the multiple data buffers, the read-only protection for the fenced slab;
- and
- performing, by the processor and when the faulting address is the address for one of the multiple data buffers, a single step processing routine for the program code instruction.
A device, comprising:
- a memory to store a plurality of instructions;
- and
- a processor to execute instructions in the memory to:
- identify, based on a program code instruction, an attempted write access operation to a fenced memory slab, where the fenced memory slab includes an alternating sequence of data buffers and guard buffers;
- invoke, based on the attempted write access operation, a page fault operation;
- perform, when a faulting address of the attempted write operation is not an address for one of the multiple data buffers, a panic routine;
- and
- perform, when the faulting address of the attempted write operation is an address for one of the multiple data buffers, a single step processing routine for the program code instruction.
A non-transitory computer-readable memory comprising computer-executable instructions, the computer-readable memory comprising:
- one or more instructions to identify, based on a program code instruction, an attempted write access operation to a fenced memory slab, where the fenced memory slab includes an alternating sequence of data buffers and guard buffers;
- one or more instructions to assign read-only protection to the fenced slab;
- one or more instructions to invoke, based on the attempted write access operation, a page fault operation;
- one or more instructions to perform, when a faulting address of the attempted write operation is not an address for one of the data buffers, a panic routine;
- one or more instructions to remove, when the faulting address of the attempted write operation is an address for one of the data buffers, the read-only protection for the fenced slab;
- one or more instructions to perform, when the faulting address of the attempted write operation is an address for one of the data buffers, a single step processing routine for the program code instruction;
- and
- one or more instructions to re-assign, after the single step processing routine, the read-only protection to the fenced slab.
Dependencies are inferred from the claim text.