Word-serial cyclic code encoder
AssigneeMarvell International Ltd.
InventorChengKuo Huang
Life of this patent
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Abstract
A cyclic code encoding device or encoder that contains word registers rather than single bit registers, and can process input bits and parity bits as input words and parity words. The cyclic code encoder can add input words to output register words, generating a feedback word, which can be supplied through a feedback loop that selectively transmits feedback words through weight arrays and intra-register adders, to the input of word registers. A controller can operate the cyclic code encoder in either an input mode or an output mode during which feedback words can be sequentially transmitted on the feedback loop and the states of the word registers can be updated and the final states of the word registers can be sequentially shifted out of the output word register as parity words.
Claims20
An encoder configured to encode cyclic codes, the encoder comprising:
- an adder coupled to an output of a first register, the adder being configured to receive input words from the first register and to output corresponding feedback words;
- a feedback loop configured to selectively transmit the feedback words to an input of a second register and an input of a first adder array that is coupled between an input of the first register and an output of the second register;
- and
- a controller configured to cause the encoder to operate in an input mode, during the input mode, the feedback words are sequentially transmitted on the feedback loop, a number of bits per a feedback word being different from a word width of at least one of the first and second registers, and states of the first register and the second register are updated.
A method for encoding cyclic codes, the method comprising:
- receiving input words from a first register coupled with an adder;
- outputting, by the adder, feedback words corresponding to the input words;
- transmitting selectively, by a feedback loop, the feedback words to an input of a second register and an input of a first adder array that is coupled between an input of the first register and an output of the second register;
- and
- causing the encoder, by a controller, to operate in an input mode, during the input mode, sequentially transmitting the feedback words on the feedback loop, a number of bits per a feedback word being different from a word width of at least one of the first and second registers, and updating states of the first register and the second register.
Dependencies are inferred from the claim text.