Data interleaver
AssigneeFreescale Semiconductor, Inc.
InventorsMohit K. Prasad, Clark H. Jarvis
Life of this patent
Estimating the term…
Abstract
Methods and corresponding systems in an interleaver include loading K symbol data, in a linear order, into a matrix memory having (R·C) storage locations corresponding R rows and C columns. A sequence of interleaved addresses is produced for reading the K symbol data in an interleaved order from the matrix memory. Next, (R·C)−K interleaved addresses are queued in a first-in-first-out (FIFO) memory. After queuing (R·C)−K interleaved addresses in the FIFO memory, symbol data is output using the interleaved addresses in the FIFO memory to address and output the symbol data in the matrix memory in the interleaved order. The FIFO memory can contain at least 234 memory locations.
Claims20
A method in an interleaver comprising:
- loading K symbol data, in a linear order, into a matrix memory having (R·C) storage locations corresponding to R rows and C columns;
- queuing symbol-related data in a first-in-first-out (FIFO) memory, wherein the symbol-related data is queued in an interleaved order;
- and
- after queuing (R·C)−K symbol-related data in the FIFO memory, outputting, before all symbol related data has been queued in the FIFO memory, the symbol data, in interleaved order, using the symbol-related data from the FIFO memory.
An interleaver comprising:
- a controller;
- a matrix memory for providing storage locations for K symbol data configured in R rows and C columns, wherein K, R, and C are integers and K≦(R·C);
- a linear address generator coupled to the controller and the matrix memory for generating addresses of the storage locations for storing the K symbol data in the matrix memory in a linear order;
- a first-in-first-out (FIFO) memory coupled to the controller and the matrix memory;
- an interleaved address generator, coupled to the controller and the FIFO memory, for generating and storing addresses of the storage locations in the FIFO memory in an interleaved order;
- and
- a filler address detector coupled to the controller and the interleaved address generator for detecting an address of filler data in the matrix memory and in response thereto preventing loading of the address of the filler data in the FIFO memory, wherein the controller is configured to control storing the K symbol data in the matrix memory in the linear order, and outputting the K symbol data from the matrix memory in the interleaved order without a delay between outputting each of the K symbol data in response to the interleaved address generator generating an address of filler data in the matrix memory wherein the outputting the K symbol data begins after (R·C)−K and prior to all K of the addresses of the storage locations in the FIFO memory have been generated and stored.
A method in an interleaver comprising:
- loading K symbol data in a linear order in a matrix memory configured as R rows and C columns, wherein K, R, and C are integers;
- producing a sequence of interleaved addreses for reading the K symbol data in an interleaved order from the matrix memory;
- queuing (R·C)−K interleaved addresses in FIFO memory;
- and
- after queuing the (R·C)−K interleaved addresses and before queuing all interleaved addresses in the FIFO memory, using the interleaved addresses from the FIFO memory to address and output the symbol data in the matrix memory in the interleaved order.
Dependencies are inferred from the claim text.