Transceiver that serves LDPC codewords for decoding including clock cycle budgeting based on block transmission length
AssigneeIntel Corporation
InventorIlan Sutskover
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Abstract
An embodiment of the present invention provides an apparatus, including a transceiver operable for communication using LDPC codes for error correction, the transceiver adapted to use an LDPC decoder that acts as a server to serve all LDPC codewords contained in at least one block transmission, and wherein the LDPC decoder consumes a certain number of clock cycles per decoding of a single codeword and a length of the block dictates a clock cycles budget that the server can use.
Claims20
An apparatus, comprising:
- a transceiver operable for communication using LDPC codes for error correction, said transceiver adapted to use an LDPC decoder that acts as a server to serve all LDPC codewords contained in at least one block transmission;
- and
- wherein said LDPC decoder consumes a certain number of clock cycles per decoding of a single codeword and a length of said at least one block transmission dictates a clock cycles budget that said LDPC decoder can use.
A method, comprising:
- using LDPC codes for error correction in a transceiver and adapting said transceiver to use an LDPC decoder that acts as a server to serve all LDPC codewords contained in at least one block transmission;
- and
- wherein said LDPC decoder consumes a certain number of clock cycles per decoding of a single codeword and a length of said least one block transmission dictates a clock cycles budget that said LDPC decoder can use.
A non-transitory computer readable medium encoded with computer executable instructions, which when accessed, cause a machine to perform operations comprising:
- using LDPC codes for error correction in a transceiver;
- wherein said transceiver is adapted to use an LDPC decoder that acts as a server to serve all LDPC codewords contained in at least one block transmission;
- and
- wherein said LDPC decoder consumes a certain number of iterations per decoding of a single codeword and a length of said least one block transmission dictates an iteration budget that said LDPC decoder can use.
Dependencies are inferred from the claim text.