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US 8,621,304 B2Granted
Built-in self-test system and method for an integrated circuit
AssigneeHewlett-Packard Development Company, L.P.
InventorsFred Hartnett, Robert McFarland
Life of this patent
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Abstract
An integrated circuit comprises random logic communicatively coupled to a non-scannable memory array. The integrated circuit also comprises a built-in self-test (BIST) controller adapted to apply test data to the random logic and propagate the test data through the random logic to test the memory array.
Claims20
An integrated circuit, comprising:
- random logic communicatively coupled to a non-scannable memory array;
- and
- a logic built-in self-test (BIST) controller that applies test data to the random logic, the logic BIST controller to:
- propagate test data through the random logic during subsequent clock cycles, the propagation of test data including read operations to a storage element of the non-scannable memory array, wherein in response to a read to an invalid storage element, an address of a valid storage element is aliased or a predetermined fixed value is provided to output as valid data, and
- output of the test data from the random logic, wherein the outputted test data includes the valid data if the read to the invalid storage element is performed, and
- the outputted test data is compared to an expected result to test the non-scannable memory array.
3 more elements
An integrated circuit, comprising:
- means for communicatively coupling a non-scannable memory array to a random logic;
- and
- means for applying test data to the random logic and propagating the test data through the random logic during subsequent clock cycles, the propagation of test data including read and write operations to a storage element of the non-scannable memory array, wherein in response to a read to an invalid storage element, an address of a valid storage element is aliased or a predetermined fixed value is provided to output as valid data,
- the means for applying and propagating the test data further outputting the test data from the random logic, wherein the outputted test data includes the valid data if the read to the invalid storage element is performed, and the outputted test data is compared to an expected value to test the means for communicatively coupling the non-scannable memory array to the random logic.
1 more element
A test method for an integrated circuit, comprising:
- loading test data into random logic of the integrated circuit;
- propagating, with a logic built-in test (BIST) controller, the test data through the random logic during subsequent clock cycles, the propagation of test data including read and write operations to a storage element of the non-scannable memory array, wherein in response to a read to an invalid storage element, an address of a valid storage element is aliased or a predetermined fixed value is provided to output as valid data;
- outputting the test data from the random logic, wherein the outputted test data includes the valid data if the read to the invalid storage element is performed;
- and
- comparing the outputted test data to an expected value to test the non-scannable memory array of the integrated circuit.
2 more elements
An integrated circuit, comprising:
- random logic communicatively coupled to a non-scannable memory array;
- and
- a logic built-in self-test (BIST) controller to apply test data to the random logic to test the random logic, wherein the test data is written to the non-scannable memory array and read from the non-scannable memory array, and in response to a read to an invalid storage element, an address of a valid storage element is aliased or a predetermined fixed value is provided in the test data read from the non-scannable memory,
- wherein the test data read from the non-scannable memory array is compared to an expected value to detect whether a defect is present in the non-scannable memory array.
1 more element
Dependencies are inferred from the claim text.