Clock control circuitry and methods of utilizing the clock control circuitry

An integrated circuit (IC) comprising:

• a Design-For-Test (DFT) circuit coupled to receive a clock polarity control signal and at least one clock signal, the DFT circuit is operable to generate one of a default one clock signal or a default zero clock signal based on the clock polarity control signal, wherein the default one clock signal or the default zero clock signal further comprises pulses over a predefined count period;
• and
• at least one Intellectual Property (IP) block coupled to receive one of the default one clock signal or the default zero clock signal from the DFT circuit, wherein the DFT circuit comprises:
• a first multiplexer coupled to receive a clock signal, an inverted version of the clock signal, and the clock polarity control signal, wherein the first multiplexer is operable to transfer one of the clock signal or the inverted clock signal according to the clock polarity control signal.

A method to test an integrated circuit (IC) comprising:

• with a multiplexer, receiving a clock signal and static control signal;
• transferring the clock signal to a burst counter;
• sending information on a predefined count period to the burst counter;
• outputting a first signal from the burst counter for the predefined count period;
• outputting a second signal from the burst counter after the predefined count period;
• sending the clock signal to the integrated circuit for the predefined count period in response to the first signal;
• and
• sending the static control signal to the integrated circuit after the predefined count period in response to the second signal.