Device and method for testing semiconductor device
AssigneeSamsung Electronics Co., Ltd.
InventorJung Rae Kim
Life of this patent
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Abstract
A device for testing a semiconductor memory device, the device including a code table that is configured to store at least a first received code and a second received code received via a host interface, a pattern generation engine that is configured to determine a third code based on at least one of the first and the second received codes stored in the code table and to output the third code, in response to a request to perform a test operation, received via the host interface, and a signal generation unit that is configured to generate control signals for testing the semiconductor memory device, based on the third code received from the pattern generation engine.
Claims21
A device for testing a semiconductor memory device, the device comprising:
- a code table configured to store at least a first received code and a second received code received via a host interface;
- a pattern generation engine configured to determine a third code based on at least one of the first and the second received codes stored in the code table and to output the third code, in response to a request to perform a test operation, received via the host interface;
- and
- a signal generator configured to generate control signals for testing the semiconductor memory device, based on the third code received from the pattern generation engine, wherein the first received code designates a combination of second codes including the second received code arranged in a predetermined sequence, and wherein the second codes correspond to different operations to be performed on the semiconductor memory device for the test operation.
A method of testing a semiconductor memory device, the method comprising:
- storing pattern codes and control codes received via a host interface;
- controlling an operation of a signal generator by determining a next control code, determining one or more pattern codes corresponding to the next control code, and outputting the one or more determined pattern codes, in response to a request to perform a test operation, received from the host interface;
- outputting a command, an address signal, and data for controlling the semiconductor memory device, based on the one or more determined pattern codes;
- and
- generating and outputting a data pattern corresponding to a read operation of the semiconductor memory device, based on the output data, wherein the next control code designates a combination of pattern codes arranged in a predetermined sequence, and wherein the pattern codes correspond to different operations to be performed on the semiconductor memory device for the test operation.
A method of testing a semiconductor memory device, the method comprising:
- receiving a plurality of codes including a first code and a second code via a host interface;
- determining a third code based on at least one of the received codes;
- outputting the third code, in response to a request to perform a test operation, received via the host interface;
- and
- generating control signals for testing the semiconductor memory device, based on the third code, wherein the first code designates a combination of second codes including the second code arranged in a predetermined sequence, and wherein the second codes correspond to different operations to be performed on the semiconductor memory device for the test operation.
Dependencies are inferred from the claim text.