Back to results
US 8,621,291 B2Granted
Semiconductor device and data processing system including the same
AssigneeElpida Memory, Inc.
InventorHiroto Kinoshita
Life of this patent
Estimating the term…
Abstract
To provide a write amplifier that is connected to bit lines, a read amplifier that is connected to the bit lines via a first switch, and a relief memory element that includes a write port that is connected to the bit lines via a second switch, and a read port that is connected to the read amplifier via a third switch. When there is a request to access a defective memory cell, during a write operation, the second switch is turned on and write data is supplied from the write amplifier to the relief memory element via the bit lines, and during a read operation, the first switch is turned off and the third switch is turned on, and then read data read from the relief memory element is supplied to the read amplifier without being routed via the bit lines.
Claims24
A semiconductor device comprising:
- a bit line that transmits write data to be written to a memory cell and read data read from the memory cell;
- a write amplifier that is connected to the bit line;
- a read amplifier that is connected to the bit line via a first switch circuit;
- a relief memory element that includes a write port and a read port, the write port being connected to the bit line via a second switch circuit, and the read port being connected to the read amplifier via a third switch circuit;
- and
- a control circuit that controls an operation of each of the first, second and third switch circuits, wherein
- the control circuit controls the second switch circuit into an electrically on state so as to supply the write data from the write amplifier to the relief memory element via the bit line in response to the memory cell being defective during a write operation, and
- the control circuit controls the first switch circuit into an electrically off state and controls the third switch circuit into an electrically on state so as to supply relief data from the relief memory element to the read amplifier in response to the memory cell being defective during a read operation.
5 more elements
A semiconductor device comprising:
- a plurality of memory cells;
- a plurality of first bit lines, a first selected one of the first bit lines is electrically connected to a selected one of the memory cells according to a first address signal;
- a second bit line to which a second selected one of the first bit lines is electrically connected according to a second address signal;
- a first switch circuit that is connected to the second bit line;
- a main amplifier that includes a first port that is connected to the second bit line, a second port that is connected to the second bit line via the first switch circuit, and a third port;
- a relief memory element that includes a first relief route and a second relief route, the first relief route being connected to the second bit line when the first relief route is activated, and the second relief route being connected to the second port of the main amplifier when the second relief route is activated;
- and
- a control circuit that is configured to access the relief memory element in response to both of the first and second address signals indicating defective addresses with the control circuit activating the first relief route of the relief memory element during a write operation and with the control circuit activating the second relief route of the relief memory element and controlling the first switch circuit into an electrically off state during a read operation so that a write data is written into the relief memory element from the third port of the main amplifier via the first port of the main amplifier, the second bit line and the first relief route of the relief memory element during the write operation and that a read data is read out from the relief memory element and supplied to the third port of the main amplifier via the second port of the main amplifier and the second relief route of the relief memory element during the read operation.
5 more elements
A semiconductor device comprising:
- a plurality of memory cells;
- an input/output line coupled to a selected one of the memory cells via a column switch circuit;
- a bus line;
- a write amplifier configured to drive, when the write amplifier is activated, the input/output line in response to a first data signal supplied from the bus line;
- a read amplifier including an input port and configured to drive, when the read amplifier is activated, the bus line in response to a second data signal supplied to the input port;
- a relief memory element;
- a first switch circuit connected between the input/output line and the input port of the read amplifier;
- a second switch circuit connected between the input/output line and the relief memory element;
- and
- a third switch circuit provided independently of each of the column switch circuit and the first and second switch circuits and connected between the relief memory element and the input port of the read amplifier.
7 more elements
Dependencies are inferred from the claim text.