Memory system that supports probalistic component-failure correction with partial-component sparing

A memory system that facilitates probabilistic error correction with partial component sparing, comprising:

• an access mechanism configured to access a block of data from the memory system, wherein each block of data in the memory system includes an array of bits logically organized into R rows and C columns, including a row-checkbit column containing row-parity bits for each of the R rows, an inner-checkbit column containing X=R−S inner checkbits and S spare bits, and C-2 data-bit columns containing data bits, wherein each column in the C columns is stored in a different memory component, and wherein the checkbits which comprise the row-parity bits and the inner checkbits, are generated from the data bits to provide guaranteed detection and probabilistic correction for a failed memory component;
• and
• an error-handling mechanism, wherein upon determining a failure for a component in the memory system has failed, the error-handling mechanism is configured to,
• examine a pattern of errors associated with the component in the memory system that has failed to determine if the failure affects a partial component associated with S or fewer bits of an associated failed column, and
• if so, correct and remap data bits from the partial component to the S spare bits in the inner-checkbit column, and after the correcting and remapping are complete, resuming accesses to the memory system with guaranteed detection and probabilistic correction of a subsequent failed memory component.

A computer system with a memory that facilitates probabilistic error correction with partial-component sparing, comprising:

• one or more processors;
• and
• a memory;
• wherein the memory includes an access mechanism configured to access a block of data from the memory system, wherein each block of data in the memory system includes an array of bits logically organized into R rows and C columns, including a row-checkbit column containing row-parity bits for each of the R rows, an inner-checkbit column containing X=R−S inner checkbits and S spare bits, and C-2 data-bit columns containing data bits, wherein each column in the C columns is stored in a different memory component, and wherein the checkbits, which comprise the row-parity bits and the inner checkbits, are generated from the data bits to provide guaranteed detection and probabilistic correction for a failed memory component;
• and
• wherein the memory includes an error-handling mechanism, wherein upon determining a failure for a component in the memory system that has failed, the error-handling mechanism is configured to,
• examine a pattern of errors associated with the component in the memory system that has failed to determine if the failure affects a partial component associated with S or fewer bits of an associated failed column, and
• if so, correct and remap data bits from the partial component to the S spare bits in the inner-checkbit column, and resume accesses to the memory system with guaranteed detection and probabilistic correction of a subsequent failed memory component.