Enhanced scalable CPU for coded execution of SW in high-dependable safety relevant applications

An electronic device, comprising:

• an encoding block configured to perform an encoding operation on a data word to generate an encoded data word having original data bits and redundant data bits;
• an original data path configured to receive one or more of the original data bits from the encoding block;
• an extended data path configured to selectively receive the redundant data bits and one or more of the original data bits from the encoding block;
• hardware extensions configured to selectively receive the redundant data bits or the original data bits from the extended data path and to selectively perform processing of extended data bits and to selectively perform coded processing of an encoded data word having redundant data bits natively in hardware;
• and
• a CPU core configured to receive original data bits from the original data path and to process the original data bits and to selectively perform a software based self-test (SBST) as a background task when the hardware extensions are performing processing of redundant data bits.

A method, comprising:

• determining an operating mode for a single channel processor core comprising hardware extensions and a CPU core;
• selectively providing redundant data bits and original data bits to the hardware extensions by way of an extended data path, based upon the operating mode;
• processing the redundant data bits natively in the hardware extensions in parallel with processing of the original data bits in the CPU core in a safety integrity operation mode;
• and
• processing one or more of the original data bits in the hardware extensions in parallel with processing one or more of the original data bits in the CPU core in a high performance operation mode.