Obfuscated hardware multi-threading

An apparatus for use in a computing device for obfuscating a multi-threaded computer program, comprising:

• a computer processor
• an instruction pipeline in the computer processor, the pipeline comprising a plurality of stages including a fetch stage for fetching computer instructions, an execution stage disposed downstream of the fetch stage for executing computer instructions and a register stage therebetween for accessing a register file, the pipeline operative for streaming first instructions of a first thread of a multi-threaded computer application program into the pipeline, the first instructions entering the pipeline at the fetch stage;
• and
• a code injector operative for detecting a stall signal indicative of a stall condition in the pipeline, and responsively to the stall signal injecting second instructions of a second thread of the multi-threaded computer application program into the pipeline, the injected second instructions entering the pipeline at an injection stage that is disposed downstream from the fetch stage up to and including the register stage for processing therein, wherein the stall condition exists at one of the stages that is located upstream from the injection stage.