Processor with support for nested speculative sections with different transactional modes

A method, comprising:

• a processor of a plurality of processors coupled to a shared memory executing a section of code comprising a plurality of protected memory access operations to the shared memory as a single atomic transaction with respect to the plurality of processors, wherein the processor is configured to execute the section of code according to a first transactional mode;
• wherein executing the section of code includes the processor executing a subsection of the section of code, wherein the processor is configured to execute the subsection according to a second transactional mode;
• and
• wherein the first and second transactional modes are each associated with different respective recovery actions that the processor is configured to perform in response to detecting an abort condition, wherein the abort condition indicates that the executing section or subsection of code is not being executed as a single atomic transaction with respect to the plurality of processors;
• wherein the recovery actions associated with the second transactional mode comprise:
• discarding any modifications to the shared memory made by one or more of the plurality of protected memory access operations of the subsection of code;
• and
• continuing execution of the subsection of code without executing any store operations of the plurality of protected memory access operations that are within the subsection of code.

An article of manufacture comprising a non-transitory computer-readable storage medium having program instructions stored thereon that, if executed by a processor in a plurality of processors that is coupled to a shared memory, cause the processor to perform a method comprising:

• initiating execution of a section of code according to a first transactional mode of the processor, wherein the first transactional mode is associated with a first set of recovery actions, wherein the section of code includes a plurality of protected memory access operations to the shared memory, and wherein execution of the section of code includes executing the plurality of protected memory access operations as a single atomic transaction with respect to the plurality of processors;
• and
• while executing the section of code, initiating execution of a subsection of the section of code according to a second transactional mode of the processor, wherein the second transactional mode is associated with a second set of recovery actions that is not identical to the first set of recovery actions;
• wherein the processor is configured to perform one or more of the second set of recovery actions in response to detecting an abort condition during execution of the subsection of code;
• and
• wherein the processor is configured to perform one or more of the first set of recovery actions in response to detecting an abort condition during execution of a portion of the section of code for which a transactional mode other than the first transactional mode is not specified;
• wherein the second set of recovery actions comprise:
• discarding any modifications to the shared memory made by one or more of the plurality of protected memory access operations of the subsection of code;
• and
• continuing execution of the subsection of code without executing any store operations of the plurality of protected memory access operations that are within the subsection of code.