US 8,621,160 B2 · System and method for contention-free memory access

Abstract

A memory control unit of a turbo code decoder includes a buffer having a plurality of storage slots, a buffer control operatively coupled to the buffer, a router operatively coupled to the buffer control and to a plurality of data sources, and a conflict detection unit operatively coupled to the router, to the buffer control, and to the plurality of data sources. The buffer temporarily stores information intended for storage in a memory bank. The buffer control determines a number of available storage slots in the buffer. The router routes data from the data sources to the buffer control. The conflict detection unit initiates a temporary halt of some of the data sources when the number of available storage slots is insufficient to store all of the data from data sources attempting to access the memory bank.

Claims22

Dependent claims

A memory control unit of a turbo code decoder comprising:

a first buffer having a plurality of storage slots, wherein the first buffer is configured to temporarily store data intended for storage in a memory bank;
a buffer control operatively coupled to the first buffer, wherein the buffer control is configured to determine a number of available storage slots in the first buffer;
a second buffer operatively coupled to a plurality of data sources, wherein the second buffer is configured to temporarily store data received from the data sources attempting to access the memory bank;
a router operatively coupled to the buffer control and to the second buffer, wherein the router is configured to route data from the second buffer to the buffer control;
and
a conflict detection unit operatively coupled to the router, to the buffer control, and to the second buffer, wherein the conflict detection unit is configured to initiate a temporary halt of the second buffer when the data received from the data sources causes multiple concurrent accesses to the memory bank.

3 more elements

An information decoder comprising:

decoders configured to collectively decode a signal according to a decoding algorithm, and to generate data therefrom;
an address generator configured to generate memory addresses for the data generated by the decoders;
a plurality of memory banks configured to store the data generated by the decoders according to the memory addresses generated by the address generator;
and
a plurality of memory control units,
wherein each of the memory control units are operatively coupled to the decoders, to one of the memory banks, and to the address generator,
wherein each of the memory control units having a plurality of storage slots configured to temporarily store data intended for storage in the one of the memory banks, and
wherein each of the memory control units are configured to:
receive data from the decoders;
determine a number of concurrent memory accesses to the one of the memory banks attempted by the decoders;
determine a maximum number of concurrent allowable memory accesses to the one of the memory banks;
and
stall a number of memory accesses that exceed the maximum number of concurrent allowable memory accesses for the one of the memory banks, and
wherein each of the decoders continue to transmit the generated data to the memory control units when the memory control units stall the number of memory accesses to the one of the memory banks.

11 more elements

Dependencies are inferred from the claim text.

System and method for contention-free memory access

Life of this patent

System and method for contention-free memory access

Life of this patent

Abstract

Claims22