Information processor system
AssigneeRenesas Electronics Corporation
InventorSeiji Miura
Life of this patent
Estimating the term…
Abstract
In an information processor system including a memory device (MEM0), a memory control device (SL0) capable of controlling an operation of the memory device, and a plurality of bus masters (MS0 to MS3) capable of giving access to the memory device through the memory control device, the memory control device includes a control circuit (SDCON) capable of giving a notice of information about a time that a data transfer from the memory device can be started to the bus master related to an access request. The bus master can cause the time information thus given to be a judgment factor as to whether an access request is given to the memory device or not. Consequently, each of the bus masters can avoid the generation of a useless access request and a data transfer to the masters to be accessed can be carried out smoothly.
Claims3
An information processor system comprising:
- a memory device;
- a memory control device capable of controlling an operation of the memory device;
- and
- a plurality of bus masters each capable of giving access to the memory device through the memory control device,
- wherein the memory control device includes a plurality of buffers,
- wherein each buffer is adapted to store an access request given from one of the bus masters,
- wherein a utilization right of each buffer is settable to a corresponding one of the plurality of bus masters,
- wherein if the utilization right of a first buffer included in the plurality of buffers is set to a first bus master included in the plurality of bus masters, the first buffer is only usable by the first bus master, and
- wherein if the utilization right of a second buffer included in the plurality of buffers is not set to any of the plurality of bus masters, the second buffer is usable by any of the plurality of bus masters.
Dependencies are inferred from the claim text.