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US 8,621,153 B2Granted
Microcode refactoring and caching
AssigneeIntel Corporation
InventorJamison D. Collins
Life of this patent
Estimating the term…
Abstract
Methods and apparatus relating to microcode refactoring and/or caching are described. In some embodiments, an off-chip structure that stores microcode is shared by multiple processor cores. Other embodiments are also described and claimed.
Claims20
A processor comprising:
- a first storage device to store a subset of microcode, the subset corresponding to a portion of the microcode, wherein the subset remains stored in the first storage device and accessible to execution logic during execution of a plurality of instructions;
- wherein a second storage device, on a different integrated circuit chip than the processor, is to store a complementary subset of the microcode that is complementary to the subset;
- and
- a first logic to determine whether a first micro-operation of the microcode is to be stored in the first storage device based at least in part on an expected frequency of access to the first micro-operation.
1 more element
A method comprising:
- storing a subset of microcode, the subset corresponding to a first plurality of micro-operations of the microcode in a first storage device, wherein the subset remains stored in the first storage device and accessible to execution logic during execution of a plurality of instructions, and wherein a second storage device, on a different integrated circuit chip than the first storage device, is to store a complementary subset of the microcode;
- and
- determining the first plurality of micro-operations to be stored in the first storage device based at least in part on an expected frequency of access to the subset of the microcode.
A system comprising:
- a first integrated circuit chip including:
- a first storage to store a subset of microcode, the subset corresponding to a portion of the microcode, wherein the subset is to remain stored in the first storage device and accessible during execution of a plurality of instructions;
- first logic to determine whether a first micro-operation of the microcode is to be included in the subset based at least in part on an expected frequency of access to the first micro-operation;
- and
- a second integrated circuit chip including a second storage, wherein the second storage is to store a complementary subset of the microcode.
2 more elements
Dependencies are inferred from the claim text.