Transparent level 2 cache that uses independent tag and valid random access memory arrays for cache access

A system, comprising:

• a processor configured to
• perform a processing task according to data stored in a main memory, and
• output each of i) a command associated with the processing task and ii) an identifier of data associated with the processing task;
• a first cache located between the processor and the main memory, the first cache configured to i) store a first portion of the data stored in the main memory, ii) receive the command, and iii) provide a first indication of whether the command has been completed at the first cache;
• and
• a second cache located between the first cache and the main memory, the second cache configured to i) store a second portion of the data stored in the main memory, ii) receive the command, and iii) provide a second indication of whether the command has been completed at the second cache,
• wherein the processor is configured to perform the processing task in response to both the first indication and the second indication being provided, and
• wherein the second cache includes:
• a command interpreter configured to i) output a cache index based on the command and the identifier, wherein the cache index identifies a location in the second cache corresponding to the second portion of the data, and ii) output a first address tag based on the command and the identifier, wherein the first address tag indicates which memory line of the second cache corresponds to the location in the second cache;
• and
• a tag storage device configured to output a second address tag based on the cache index,
• wherein the second cache is configured to i) compare the first address tag to the second address tag, and ii) selectively clear a validity value associated with the memory line based on the comparison.

A method, comprising:

• using a processor, i) performing a processing task according to data stored in a main memory, and ii) outputting each of a command associated with the processing task and an identifier of data associated with the processing task;
• using a first cache located between the processor and the main memory, i) storing a first portion of the data stored in the main memory, ii) receiving the command, and iii) providing a first indication of whether the command has been completed at the first cache;
• and
• using a second cache located between the first cache and the main memory, i) storing a second portion of the data stored in the main memory, ii) receiving the command, and iii) providing a second indication of whether the command has been completed at the second cache,
• wherein performing the processing task comprises performing the processing task in response to a signal indicating that both the first indication and the second indication were provided.

A method, comprising:

• using a processor, i) performing a processing task according to data stored in a main memory, and ii) outputting each of a command associated with the processing task and an identifier of data associated with the processing task;
• using a first cache located between the processor and the main memory, i) storing a first portion of the data stored in the main memory, ii) receiving the command, and iii) providing a first indication of whether the command has been completed at the first cache;
• using a second cache located between the first cache and the main memory, i) storing a second portion of the data stored in the main memory, ii) receiving the command, and iii) providing a second indication of whether the command has been completed at the second cache,
• wherein performing the processing task comprises performing the processing task in response to both the first indication and the second indication being provided;
• outputting a cache index based on the command and the identifier, wherein the cache index identifies a location in the second cache corresponding to the second portion of the data;
• outputting a first address tag based on the command and the identifier, wherein the first address tag indicates which memory line of the second cache corresponds to the location in the second cache;
• outputting a second address tag based on the cache index;
• comparing the first address tag to the second address tag;
• and
• selectively clearing a validity value associated with the memory line based on the comparison.