Back to results
US 8,621,148 B2Granted
Hierarchical memory architecture to connect mass storage devices
AssigneeMicron Technology, Inc.
InventorSean Eilert
Life of this patent
Estimating the term…
Abstract
A hierarchical memory storage using a concentrator device that is located between a processor and memory storage devices to provide a succession of memory devices and enable attachment of a memory depth to a processor controller with a limited pin count.
Claims22
A method of using a hierarchical memory system in which a concentrator device having a frontside bus port is coupled to a processor, the method comprising:
- concurrently coupling volatile and non-volatile mixed memory device types to a bus coupled to a number of backside ports of the concentrator device;
- coupling memory devices that are external to the number of backside ports to the bus;
- storing data from the memory devices in phase change memory (PCM) arrays located within the concentrator device;
- transferring the stored data from the memory devices to the processor through the frontside bus port;
- and
- copying the contents of the volatile memory device types prior to the volatile memory device types being powered down.
3 more elements
An apparatus, comprising:
- a multiprocessing interface to couple to a processor;
- at least one backside port to couple to a plurality of memory storage devices including volatile memory device types;
- an internal bus coupling the at least one backside port with the multiprocessing interface to transfer stored data from the plurality of memory storage devices to the processor;
- and
- a phase change memory (PCM) array located within the apparatus;
- the PCM array to copy contents of the volatile memory device types prior to the volatile memory device types being powered down.
3 more elements
An apparatus, comprising:
- a plurality of concentrator devices to couple to a processor, each of the plurality of concentrator devices including
- an interface to couple to the processor or another one of the plurality of concentrator devices;
- a plurality of backside ports being configured to couple concurrently to volatile and non-volatile mixed memory device types;
- an internal bus coupling each of the plurality of backside ports with the interface to transfer data to and from the plurality of memory storage devices to the processor;
- and
- a phase change memory (PCM) array to copy contents of the volatile memory device types prior to the volatile memory device types being powered down.
3 more elements
A method, comprising:
- concurrently coupling volatile and non-volatile mixed memory device types to a bus coupled to a number of backside ports of a concentrator device;
- transferring stored data to and from the volatile and non-volatile mixed memory device types from and to a processor through a frontside bus port of the concentrator device;
- and
- copying contents of the volatile memory device types to an internal non-volatile memory array of the concentrator device prior to the volatile memory device types being powered down.
1 more element
Dependencies are inferred from the claim text.