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US 8,621,142 B1Granted
Method and apparatus for achieving consistent read latency from an array of solid-state storage devices
AssigneeNetApp, Inc.
InventorsSteve C. Miller, Jeffrey S. Kimmel
Life of this patent
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Abstract
A technique for achieving consistent read latency from an array of non-volatile solid-state memories involves an external entity determining the “busy” or “not busy” status of non-volatile solid-state memory elements in a RAID group. An external data layout engine then uses parity based RAID data reconstruction to avoid having to read from any memory element that is busy in a RAID group, along with careful scheduling of writes and erasures.
Claims28
A storage system comprising:
- a communication interface through which to communicate with a host;
- a storage interface through which to access a plurality of solid-state memory devices arranged as an N×M array of solid-state memory elements, where M is at least three (3);
- and
- a processor which, in operation, performs a set of operations including
- performing memory access operations on the solid-state memory elements in response to requests from the host, while not permitting all of the memory elements at a time in each row of the array to perform an erase or write;
- in response to a request from the host to read a set of data, determining whether a solid-state memory element in which at least a portion of the set of data is stored is busy;
- and
- when the solid-state memory element in which at least a portion of the set of data is stored is busy, reading information from other solid-state memory elements in the array, and reconstructing the set of data from said information.
5 more elements
A network storage system comprising:
- a network interface through which to communicate with a plurality of hosts over a network;
- a storage interface through which to access a plurality of non-volatile solid-state memory devices arranged in an array comprising N rows and M columns of non-volatile solid-state memory elements, where M is at least three (3);
- and
- a processor which, in operation, performs a set of operations including
- applying a parity based redundancy scheme to a plurality of non-volatile solid-state memory elements, including defining a plurality of redundancy groups from among the plurality of non-volatile solid-state memory elements;
- permitting only a predetermined sized subset of the non-volatile solid-state memory elements in each redundancy group of the array to perform an erase or write at a time;
- in response to a request to read a set of data, identifying a non-volatile solid-state memory element in which at least a portion of the set of data is stored, wherein the identified non-volatile solid-state memory is a member of the redundancy group;
- determining whether the identified non-volatile solid-state memory element is busy;
- and
- in response to a determination that the identified non-volatile solid-state memory element is busy, reading information from other non-volatile solid-state memory elements in the redundancy group, and reconstructing the set of data from said information.
7 more elements
A method comprising:
- performing memory access operations on a group of non-volatile solid-state memory devices that includes a plurality of solid-state memory elements, including limiting the number of the solid-state memory elements in the group that are allowed to perform an erase or write at a time;
- in response to a request to read a set of data, determining whether a solid-state memory element in which at least a portion of the set of data is stored in the group is busy;
- and
- when a solid-state memory element in which at least a portion of the set of data is stored is busy, reading information from other solid-state memory elements in the group, and reconstructing the set of data from said information.
1 more element
A method comprising:
- performing memory access operations on a plurality of non-volatile solid-state memory devices arranged in an array comprising N rows and M columns of memory elements, where M is at least three (3), including permitting only a predetermined number of memory elements at a time to perform an erase or write in each row of the array, wherein the predetermined number corresponds to less than all of the memory elements in a row;
- in response to a request to read a set of data, determining whether a memory element in which at least a portion of the set of data is stored is busy;
- and
- in response to a determination that the memory element in which at least a portion of the set of data is stored is busy, reading information from other memory elements in a row of the array which contains said memory element, and reconstructing the set of data from said information.
1 more element
Dependencies are inferred from the claim text.