Semiconductor memory device and information data processing apparatus including the same

An information data processing system comprising:

• a semiconductor memory device;
• and
• a controller that is connected to said semiconductor memory device through a bus and processes information data stored in said semiconductor memory device and controls an operation of said semiconductor memory device, wherein
• said semiconductor memory device includes:
• a plurality of data input/output pins;
• a plurality of banks that each store a plurality of information data;
• a selector;
• and
• a control circuit, and wherein
• said control circuit simultaneously accesses said plurality of banks, in response to one of a read-out command or a single write-in command from outside, by way of a first access mode;
• and
• said selector coordinates said plurality of data input/output pins with said plurality of banks in a predetermined relationship by way of said first access mode.

A device comprising:

• a plurality of memory banks each including a plurality of memory cells;
• M pieces of data terminals, M being an integer more than 1;
• and
• an access circuit configured to perform a first operation in response to a data read request in a first access mode, a second operation in response to a data write request in the first access mode, a third operation in response to a data read request in a second access mode, and a fourth operation in response to a data write request in the second access mode;
• the first operation being such that first data including M bits are read out from a selected one of the memory banks, and the M bits of the first data are transferred respectively to the data terminals in parallel to each other;
• the second operation being such that second data including M bits are transferred respectively from the data terminals in parallel to each other, and the second data are written into a selected one of the memory banks;
• the third operation being such that third data including M bits are read out from the memory banks, respectively, each of the M bits being stored in a different one of the memory banks, and the third data are transferred respectively to the data terminals in parallel to each other, respectively;
• and
• the fourth operation being such that fourth data including M bits are transferred respectively from the data terminals in parallel to each other, respectively, and the fourth data are written into the memory banks, each of the M bits of the fourth data being written into a different one of the memory banks.

A device comprising:

• a plurality of memory banks each including a plurality of memory cells;
• M pieces of data terminals, M being an integer more than 1;
• and
• a control circuit configured to perform a first operation in response to a data read request in a first access mode, a second operation in response to a data write request in the first access mode, a third operation in response to a data read request in a second access mode, and a fourth operation in response to a data write request in the second access mode;
• the first operation being such that first data including M bits are read out from a selected one of the memory banks, and the M bits of the first data are transferred respectively to the data terminals in parallel to each other;
• the second operation being such that second data including M bits are transferred respectively from the data terminals in parallel to each other, and the second data are written into a selected one of the memory banks;
• the third operation being such that a plurality of sets of third data are read out from the memory banks, each of the sets of third data including M bits and being read out from a different one of the memory banks, and the sets of third data are transferred to the data terminals one set by one set in series;
• and
• the fourth operation being such that a plurality of sets of fourth data are transferred from the data terminals one set by one set in series, each of the sets of fourth data including M bits, and each of the sets of fourth data is written into a different one of the memory banks.