Uniform multi-chip identification and routing system
AssigneeAdvanced Micro Devices, Inc.
InventorsGabriel H. Loh, Bradford M. Beckmann, Jaewoong Chung, Subho Chatterjee
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Abstract
Various methods, computer-readable mediums, articles of manufacture and systems are disclosed. In one aspect, a method is provided that includes generating a packet with a first semiconductor chip. The packet is destined to transit a first substrate and be received by a node of a second semiconductor chip. The packet includes a packet header and packet body. The packet header includes an identification of a first exit point from the first substrate and an identification of the node. The packet is sent to the first substrate and eventually to the node of the second semiconductor chip.
Claims21
A method, comprising:
- generating a packet with a first semiconductor chip, the packet destined to transit a first substrate and be received by a node of a second semiconductor chip, the packet including a packet header and packet body, the packet header including an identification of a first exit point from the first substrate and an identification of the node;
- and
- sending the packet to the first substrate.
A computer readable medium having computer-executable instructions for performing a method comprising:
- generating a packet with a first semiconductor chip, the packet destined to transit a first substrate and be received by a node of a second semiconductor chip, the packet including a packet header and packet body, the packet header including an identification of a first exit point from the first substrate and an identification of the node;
- and
- sending the packet through the first substrate to the node of the second semiconductor chip.
An article of manufacture, comprising:
- a computer-readable medium having stored thereon a data structure;
- and
- a packet including packet header and a packet body and destined to transit from a first semiconductor chip through a first substrate and be received by a node of a second semiconductor chip, the packet header including an identification of a first exit point from the first substrate and an identification of the node.
A system, comprising:
- a first substrate;
- a first semiconductor chip coupled to the first substrate and having a node;
- and
- a second semiconductor chip coupled to the first substrate and programmed to generate and send a packet through the first substrate to the node of the first semiconductor chip, the packet including a packet header and packet body, the packet header including an identification of a first exit point from the first substrate and an identification of the node.
Dependencies are inferred from the claim text.