US 8,621,127 B2Granted

Multi-processor device with groups of processors and respective separate external bus interfaces

AssigneeRenesas Electronics Corporation

InventorKoichi Ishimi

Life of this patent

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Abstract

The present invention intends to provide a high-performance multi-processor device in which independent buses and external bus interfaces are provided for each group of processors of different architectures, if a single chip includes a plurality of multi-processor groups. A multi-processor device of the present invention comprises a plurality of processors including first and second groups of processors of different architectures such as CPUs, SIMD type super-parallel processors, and DSPs, a first bus which is a CPU bus to which the first processor group is coupled, a second bus which is an internal peripheral bus to which the second processor group is coupled, independent of the first bus, a first external bus interface to which the first bus is coupled, and a second external bus interface to which the second bus is coupled, over a single semiconductor chip.

Claims13

Dependent claims

A semiconductor device comprising:

a plurality of processors formed over a single chip and including a plurality of a first type of processors disposed in a first layout region of the single chip in plan view and a plurality of a second type of processors disposed separately from the plurality of the first, type of processors in a second layout region of the single chip in plan view, each said first type of processor having a first architecture, and each said second type of processor having a second architecture which is different from the first architecture of said first type of processor;
a first bus which is disposed in the first layout region of the single chip and to which each of the plurality of the first type of processors is coupled;
a second bus which is disposed in the first layout region of the single chip and to which each of the plurality of the second type of processors is coupled;
a first external bus interface to which the first bus is coupled;
a second external bus interface to which the second bus is coupled;
a plurality of first voltage supply lines arranged along one direction in the first layout region of the single chip in plan view with a space of a first width between adjacent ones of said first voltage supply lines, each said first voltage supply line having a second width in said one direction;
and
a plurality of second voltage supply lines arranged along said one direction in the second layout region of the single chip in plan view with a space of a third width, which is larger than the first width, between adjacent ones of said second voltage supply lines, each said second voltage supply line having a fourth width, which is smaller than the second width, in said one direction,
wherein, in plan view, the first external bus interface is disposed at a first edge of the single chip and the second external bus interface is disposed at a second edge of the single chip different from the first edge,
wherein the plurality of the first type of processors and the plurality of the second type of processors are controlled using separate clocks which differ in frequency or phase,
wherein the first external bus interface is coupled to a first external bus and the second external bus interface is coupled to a second external bus,
wherein the plurality of the first type of processors are configured to access the first external bus via the first bus and the first external bus interface and to access the second external bus via the first bus, the second bus, and the second external bus interface, and
wherein the plurality of the second type of processors are configured to access the second external bus via the second bus and the second external bus interface.

10 more elements

A semiconductor device comprising:

a plurality of a first type of processors disposed in a first layout region of a single chip in plan view, the single chip having a rectangular shape with four sides in plan view;
a plurality of a second type of processors disposed separately from the plurality of the first type of processors in a second layout region of the single chip in plan view, each said second type of processor having a different architecture from said first type of processor;
a first bus provided over the single chip, and being disposed in the first layout region of the single chip in plan view and to which the plurality of the first type of processors is coupled;
a second bus provided over the single chip, and being disposed in the second layout region of the single chip in plan view and to which the plurality of the second type of processors is coupled;
a first external bus interface provided over the single chip, to which the first bus is coupled;
a second external bus interface provided over the single chip, to which the second bus is coupled;
a plurality of first voltage supply lines arranged along one direction in the first layout region of the signal chip in plan view with a space of a first width between adjacent ones of said first voltage supply lines, each first voltage supply line having a second width in said one direction;
and
a plurality of second voltage supply lines arranged along said one direction in the second layout region of the single chip in plan view with a space of a third width, which is larger than the first width, between adjacent ones of said second voltage supply lines, each said second voltage supply line having a fourth width, which is smaller than the second width, in said one direction,
wherein, in plan view, the first external bus interface has a portion disposed closer to a first side of the four sides of the single chip than to the other three sides, and the second external bus interface has a portion disposed closer to a second side of the four sides of the single chip than to the other three sides, said second side being a different side from the first side,
wherein the plurality of the first type of processors and the plurality of the second type of processors are controlled using separate clocks which differ in frequency or phase,
wherein the first external bus interface is coupled to a first external bus and the second external bus interface is coupled to a second external bus,
wherein the plurality of the first type of processors are configured to access the first external bus via the first bus and the first external bus interface and to access the second external bus via the first bus, the second bus, and the second external bus interface, and
wherein the plurality of the second type of processors are configured to access the second external bus via the second bus and the second external bus interface.

11 more elements

Dependencies are inferred from the claim text.

Facts

Application: 13/471,968Filed 15 May 2012 · continuation
Priority: JP 2007-01136722 Jan 2007
Published: US 2012/0226847 A16 Sep 2012
Granted: 31 Dec 2013
Term ends: Not estimatedThe source records don’t support an estimate.

Classification12 codes

G06F 13/4031
Using bus bridges: with arbitration
G06F 1/08
Generating or distributing clock signals or signals derived directly therefrom: clock generators with changeable or programmable clock frequency
G06F 1/3293
Power saving characterised by the action undertaken: by switching to a less power-consuming processor, e.g. sub-CPU
G06F 9/3887
Using a plurality of independent parallel functional units: controlled by a single instruction for multiple data lanes [SIMD]

Family

Application11/970,732Parent of this continuation · filed 8 Jan 2008
US 2012/0226847 A1Pre-grant publication · published 6 Sep 2012
US 8,200,878 B2Parent of this continuation
US 2008/0282012 A1Published application
US 8,621,127 B2This patent

From the US filing history. Foreign family members aren’t listed.