Leading sign digit predictor for floating point near subtractor

A method for performing an effective subtraction of two floating point inputs each having an unsigned magnitude mantissa and an exponent, the method comprising:

• determining a first of the two inputs has an exponent that is one larger than the exponent of a second of the two inputs;
• zero-extending by one bit, left-shifting by one bit, and inverting the mantissa of one of the two inputs that has an exponent that is one larger than the exponent of the other of the two inputs to produce a first addend;
• zero-extending by one bit the mantissa of the other of the two inputs to produce a second addend;
• adding the first and second addends, wherein said adding produces a negative difference in response to said zero-extending by one bit, left-shifting by one bit, and inverting the mantissa of the one of the two inputs that has an exponent that is one larger than the exponent of the other of the two inputs to produce a first addend and said zero-extending by one bit the mantissa of the other of the two inputs to produce a second addend;
• inverting the negative difference to produce an unnormal mantissa;
• performing a Boolean NAND (NOT-AND) function on the first and second addends to produce a prediction string;
• and
• left-shifting the unnormal mantissa by a shift amount based on the prediction string to produce a normalized mantissa result;
• wherein the method is performed by an integrated circuit.

An apparatus for predicting leading sign digits in a negative difference, the apparatus comprising:

• a comparator, configured to determine a larger of two numbers that differ in magnitude by not more than one digit position, wherein the larger of the two numbers is designated as the subtrahend and the smaller as the minuend;
• wires and logic, configured to align the subtrahend relative to the minuend by the not more than one digit position and to invert the aligned subtrahend;
• and
• a plurality of NAND (NOT-AND) gates, configured to perform a Boolean NAND function of corresponding digits of the minuend and the aligned inverted subtrahend to produce a prediction string of bits, wherein a zero value is assigned to the most significant bit of the prediction string;
• wherein a string of leading zeros of the prediction string predicts a corresponding string of leading sign digits of a negative difference of the minuend and aligned subtrahend.

A method for predicting leading sign digits in a negative difference, the method comprising:

• determining a larger of two numbers that differ in magnitude by not more than one digit position;
• designating the larger of the two numbers as the subtrahend and the smaller as the minuend;
• aligning the subtrahend relative to the minuend by the not more than one digit position;
• inverting the aligned subtrahend;
• performing a Boolean NAND (NOT-AND) function of corresponding digits of the minuend and the aligned inverted subtrahend to produce a prediction string of bits;
• assigning a zero value to the most significant bit of the prediction string;
• and
• predicting a string of leading sign digits of a negative difference of the minuend and aligned subtrahend by a corresponding string of leading zeros of the prediction string;
• wherein the method is performed by an integrated circuit.

An apparatus for predicting leading sign digits in a negative difference, the apparatus comprising:

• comparison logic, configured to determine a larger of two numbers that differ in magnitude by not more than one digit position, wherein the larger of the two numbers is designated as the subtrahend and the smaller as the minuend;
• wires and logic, configured to align the subtrahend relative to the minuend by the not more than one digit position and to invert the aligned subtrahend;
• an arithmetic unit, configured to generate a negative difference in response to the minuend and the aligned inverted subtrahend;
• and
• a leading sign digit predictor, configured to produce a prediction of leading sign digits of the negative difference in response to the minuend and the aligned inverted subtrahend.

A method for predicting leading sign digits in a negative difference, the method comprising:

• determining a larger of two numbers that differ in magnitude by not more than one digit position;
• designating the larger of the two numbers as the subtrahend and the smaller as the minuend;
• aligning the subtrahend relative to the minuend by the not more than one digit position;
• inverting the aligned subtrahend;
• presenting the minuend and the aligned inverted subtrahend to a binary adder to produce a negative difference;
• and
• presenting the minuend and the aligned inverted subtrahend to a leading sign digit predictor to produce a prediction of leading sign digits of the negative difference;
• wherein the method is performed by an integrated circuit.