Method of performing a simulation of a design under test and a circuit for enabling testing of a circuit design

A method of performing a simulation of a design under test, the method comprising:

• generating the design under test in an integrated circuit, wherein an input block having an adjustable output width implemented in the integrated circuit is coupled to an input of the design under test and an output block having the adjustable input width implemented in the integrated circuit is coupled to an output of the design under test, wherein the input block is configured with an output having a first width corresponding to an input requirement for the design under test;
• receiving test data of an input frame of bits having an arbitrary dimension;
• coupling the test data to the input block using a simulation engine;
• transforming the test data of the input frame of bits to conform to the input requirement for the design under test;
• buffering the test data of the input frame of bits in the input block, wherein the buffered test data comprises a multi-dimensional sample that includes scalar values;
• generating, by way of the input block, an input signal comprising the buffered test data for the design under test by scanning the buffered test data in a pre-defined order, wherein the input signal comprises individual scalar values that are extracted from the scalar values of the buffered test data and provided to the input of the design under test having the first width corresponding to the input requirement for the design under test;
• and
• coupling the output of the design under test to the output block according to an output requirement of the design under test.

A circuit for enabling testing of a circuit design implemented in an integrated circuit, the circuit comprising:

• a design under test implemented in the integrated circuit, the design under test having an input port comprising a first data width and an output port comprising a second data width;
• an input block coupled to the design under test, the input block having an input for receiving test data of an input frame of bits of an arbitrary dimension and having an adjustable output width, wherein the input block is configured to have an output of the first data width corresponding to an input requirement of the design under test for coupling the test data having the first data width to the input port of the design under test, the input block buffering the test data and transforming the test data of the input frame of bits to conform to the input requirement of the design under test, wherein the buffered test data includes a multi-dimensional sample that contains scalar values, and wherein the test data having the first data width coupled to the input port of the design under test comprises individual scalar values that are extracted from the scalar values of the buffered test data by a scanning of the buffered test data in a predefined order;
• and
• an output block coupled to the design under test, the output block having an adjustable input width for receiving output data from the output port of the design under test at an input port comprising the second data width.