US 8,619,979 B2Granted

Physically unclonable function implemented through threshold voltage comparison

AssigneeInternational Business Machines Corporation

InventorsJoel T. Ficke, William E. Hall, Terence B. Hook, Michael A. Sperling, Larry Wissel

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Abstract

Electronic devices and methods are disclosed to provide and to test a physically unclonable function (PUF) based on relative threshold voltages of one or more pairs of transistors. In a particular embodiment, an electronic device is operable to generate a response to a challenge. The electronic device includes a plurality of transistors, with each of the plurality of transistors having a threshold voltage substantially equal to an intended threshold voltage. The electronic device includes a challenge input configured to receive the challenge. The challenge input includes one or more bits that are used to individually select each of a pair of transistors of the plurality of transistors. The electronic device also includes a comparator to receive an output voltage from each of the pair of transistors and to generate a response indicating which of the pair of transistors has the higher output voltage. The output voltage of each of the pair of transistors varies based on the threshold voltage of each of the pair of transistors.

Claims18

Dependent claims

An electronic device having selectable transistor pairs configured to generate a response to a challenge, the electronic device comprising:

a plurality of transistors, each of the plurality of transistors having a threshold voltage substantially equal to an intended threshold voltage;
a challenge input configured to receive the challenge, wherein the challenge input includes one or more bits that are used to individually select a first transistor of the plurality of transistors and a second transistor of the plurality of transistors;
a comparator configured to:
receive a first output voltage from the first transistor;
receive a second output voltage from the second transistor;
receive an offset voltage;
generate a first response indicating which of the first transistor and the second transistor has a higher output voltage based on a comparison of the first output voltage and the second output voltage, wherein the first output voltage and the second output voltage vary as a result of a variation in the threshold voltages of the first transistor and the second transistor;
and
generate a second response, wherein the second response differs from the first response when a sum of the offset voltage and a lower voltage of the first output voltage and the second output voltage is greater than or equal to a higher voltage of the first output voltage and the second output voltage and wherein the second response is the same as the first response when the sum is less than the higher voltage;
a reference voltage source configured to:
supply a reference voltage that is substantially equal to the intended threshold voltage to a first gate of the first transistor, and
supply the reference voltage to a second gate of the second transistor;
wherein the first output voltage results from a current flowing from a common drain voltage source across a first resistor having a common resistance value when the reference voltage is applied to the first gate;
and
wherein the second output voltage results from the current flowing from the common drain voltage source across a second resistor having the common resistance value when the reference voltage is applied to the second gate.

12 more elements

A method of providing an electronic device with selectable transistor pairs configured to generate a response to a challenge, the method comprising:

supplying a reference voltage substantially equal to an intended threshold voltage to gates of a plurality of transistors, each of the plurality of transistors having a threshold voltage substantially equal to the intended threshold voltage;
selecting, at a selector, a first transistor and a second transistor of the plurality of transistors in response to a challenge including a combination of selection bits;
receiving, at a differential amplifier, a first output voltage of the first transistor, a second output voltage of the second transistor, and an offset voltage;
generating, at the differential amplifier, a first response to the challenge in response to determining which of the first transistor and the second transistor has a higher output voltage based on a comparison of the first output voltage and the second output voltage, wherein the first output voltage and the second output voltage are positive and wherein the first output voltage and the second output voltage vary as a result of a variation in threshold voltages of the first transistor and the second transistor;
generating, at the differential amplifier, a second response to the challenge, wherein the second response differs from the response when a sum of the offset voltage and a lower voltage of the first output voltage and the second output voltage is greater than or equal to a higher voltage of the first output voltage and the second output voltage and wherein the second response is the same as the first response when the sum is less than the higher voltage;
wherein a drain of the first transistor is connected to a common drain voltage via a first resistor having a common resistance value, wherein the first output voltage includes a voltage across the first resistor when the reference voltage is applied to a gate of the first transistor;
and
wherein a drain of the second transistor is connected to the common drain voltage via a second resistor having the common resistance value, wherein the second output voltage includes a voltage across the second resistor when the reference voltage is applied to a gate of the second transistor.

5 more elements

A method comprising:

sending a challenge to a device, wherein in response to the challenge a first transistor and a second transistor are selected from a plurality of transistors included in the device and wherein each of the plurality of transistors is configured to have a threshold voltage substantially equal to an intended threshold voltage;
receiving a first response indicating which of a first output voltage of the first transistor and a second output voltage of the second transistor is higher based on a comparison of the first output voltage and the second output voltage, wherein the first output voltage and the second output voltage are positive;
receiving a second response, wherein the second response differs from the first response when a first sum of a first offset voltage and a lower voltage of the first output voltage and the second output voltage is greater than or equal to a higher voltage of the first output voltage and the second output voltage and wherein the second response is the same as the first response when the first sum is less than the higher voltage;
comparing the first response to the second response, wherein a transistor pair of the first transistor and the second transistor is identified as unstable when the first response and the second response are different;
masking the transistor pair as unusable in authenticating the device in response to identifying the transistor pair as unstable;
recording the first response when the transistor pair is not identified as unstable;
wherein a drain of the first transistor is connected to a common drain voltage via a first resistor having a common resistance value, wherein the first output voltage includes a voltage across the first resistor when the reference voltage is applied to a gate of the first transistor;
and
wherein a drain of the second transistor is connected to the common drain voltage via a second resistor having the common resistance value, wherein the second output voltage includes a voltage across the second resistor when the reference voltage is applied to a gate of the second transistor.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 12/823,278Filed 25 Jun 2010
Published: US 2011/0317829 A129 Dec 2011
Granted: 31 Dec 2013
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

G06F 21/73
To assure secure computing or processing of information: by creating or determining hardware identification, e.g. serial numbers
H04L 9/3278
Using challenge-response: using physically unclonable functions [PUF]
H04L 9/08
Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols: key distribution or…
H04L 9/0866
Generation of secret information including derivation or calculation of cryptographic keys or passwords: involving user or device identifiers,…