US 8,619,975 B2Granted

Cipher processing apparatus

AssigneeFujitsu Limited

InventorsDai Yamamoto, Kouichi Itoh, Jun Yajima

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Abstract

A cipher processing apparatus for arithmetic operations of an FO function and an FL function comprising: an FL function operating unit for generating a 2N-bit output based on a first extension key; a partial function operating unit for generating an N-bit output based on second and third extension keys; an N-bit intermediate register for storing an output of the partial operating unit; a 2N-bit first data register for storing data based on the output of the FL function operating unit; and a controller for making the partial function operating unit perform six cycles, inputting an output of the intermediate register to the FL function operating unit, and storing the data based on the output of the FL function operating unit in the first data register, in a first case in which the FL function uses a result of an arithmetic operation of the FO function.

Claims19

Dependent claims

A cipher processing apparatus for arithmetic operations of an FO function and an FL function in a cipher process, comprising:

a first circuitry configured to generate a 2N-bit output by an arithmetic operation of the FL function based on a 2N-bit input and a first extension key;
a second circuitry configured to generate an N-bit output by an arithmetic operation of a partial function of an FI function based on an N-bit input and second and third extension keys;
an N-bit intermediate register configured to store an output of the second circuitry;
a 2N-bit first data register configured to store data based on the output of the first circuitry;
a controller configured to make the second circuitry perform six cycles of the arithmetic operation of the partial function, inputting an output of the N-bit intermediate register to the first circuitry, and storing the data based on the output of the first circuitry in the 2N-bit first data register, in a first case in which the FL function uses a result of an arithmetic operation of the FO function;
and
a third circuitry configured to generate a correction bit string of 2N bits based on the first extension key,
wherein the controller makes the first circuitry perform the arithmetic operation of the FL function even numbers of times, executes an XOR operation between the correction bit string generated by the third circuitry and the output of the first circuitry, and stores a result of the XOR operation in the first data register, in the first case,
wherein N is a number greater than 0.

6 more elements

A cipher processing method for arithmetic operations of an FO function and an FL function in a cipher process, comprising:

generating a 2N-bit output using an arithmetic operation of the FL function based on a 2N-bit input and a first extension key by a first circuitry;
generating an N-bit output using an arithmetic operation of a partial function of an FI function based on an N-bit input and second and third extension keys by a second circuitry;
storing an output of the second circuitry in an N-bit intermediate register;
storing data based on the output of the first circuitry in a 2N-bit first data register;
making the second circuitry perform six cycles of the arithmetic operation of the partial function, inputting an output of the N-bit intermediate register to the first circuitry, and storing the data based on the output of the first circuitry in the 2N-bit first data register, by a controller, in a first case in which the FL function uses a result of an arithmetic operation of the FO function;
generating a correction bit string of 2N bits based on the first extension key;
making the first circuitry perform the arithmetic operation of the FL function even numbers of times;
executing an XOR operation between the correction bit string generated by a third circuitry and the output of the first circuitry;
and
storing a result of the XOR operation in the first data register, in the first case,
wherein N is a number greater than 0.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application: 12/656,018Filed 13 Jan 2010
Priority: JP 2009-725016 Jan 2009
Published: US 2010/0183144 A122 Jul 2010
Granted: 31 Dec 2013
Term ends: Not estimatedThe source records don’t support an estimate.

Classification3 codes

H04L 9/0625
Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation: with splitting of the data…
H04L 2209/122
Details relating to cryptographic hardware or logic circuitry: hardware reduction or efficient architectures
H04L
Digital communication