Clock generation devices and methods
AssigneeMediatek Inc.
InventorsKuan-Hua Chao, Chuan Liu, Tse-Hsiang Hsu
Life of this patent
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Abstract
A clock generation device provided for a transmitter is provided and comprises a clock generator, a calculator and a first phase locked loop (PLL) circuit. The clock generator generates a first clock signal. The calculator calculates a frequency difference between the first and second clock signals. The first PLL circuit generates an output clock signal according to a first reference clock signal related to the first clock signal, and a frequency of the output clock signal is changed according to the frequency difference. The transmitter transmits data according to the output clock signal.
Claims14
A clock generation device provided for a transmitter, wherein the transmitter transmits data according to an output clock signal, the clock generation device comprising
- a clock generator for generating a first clock signal;
- a calculator for calculating a frequency difference signal representing a frequency difference between the first clock signal and a second clock signal;
- a first phase locked loop (PLL) circuit for generating the output clock signal based on the first clock signal and the frequency difference signal, wherein a frequency of the output clock signal is changed according to the frequency difference signal;
- and
- a second PLL circuit for generating a third clock signal according to the first clock signal and adjusting a frequency of the third clock signal according to the frequency difference signal, wherein the first PLL circuit is arranged to receive the third clock signal serving as a first reference clock signal.
A clock generation method for a transmitter, wherein the transmitter transmits data according to an output clock signal provided from a clock generation device, the clock generation method comprising:
- generating a first clock signal by an on-board clock source of the clock generation device, wherein the on-board clock source is implemented by a crystal or resonator;
- receiving the first clock signal, by a PLL circuit of the clock generation device, to serve as a reference clock signal of the PLL circuit;
- and
- generating the output clock signal, by the PLL circuit, based on both the reference clock signal and a frequency difference, wherein the frequency difference between the reference clock signal and a second clock signal is calculated in manufacturing or testing of the clock generation device before leaving factory for calibration of a frequency of the output clock signal, and wherein the second clock signal is provided from an external device outside the clock generation device.
A data transmission method for a transmitter, comprising:
- receiving a first clock signal from an on-board clock source, by a PLL circuit of a clock generation device, to serve as a reference clock signal of the PLL circuit;
- generating an output clock signal, by the PLL circuit, based on the reference clock signal;
- calibrating, by the clock generation device, a frequency of the output clock signal for the transmitter according to a frequency difference to generate a calibrated output clock signal;
- and
- transmitting data, by the transmitter, according to the calibrated output clock signal;
- wherein the frequency difference is calculated as a difference between a precise clock signal and the reference clock signal in manufacturing or testing of the clock generation device before leaving factory, and the on-board clock source is implemented by a crystal or resonator.
An integrated circuit embodying a clock generation device, the clock generation device comprising:
- a clock generator for generating a first clock signal, wherein the clock generator is implemented by a crystal or resonator;
- a storage unit for storing a frequency difference between the first clock signal and a second clock signal, and
- a PLL circuit for receiving the first clock signal to serve as a reference clock signal and generating an output clock signal based on the reference clock signal and the stored frequency difference;
- wherein the stored frequency difference is calculated as a difference between the reference clock signal and a second clock signal in manufacturing or testing of the clock generation device before leaving a factory;
- and
- wherein the second clock signal is supplied by an external device, and the external device not being a part of the integrated circuit and being independent of a receiver circuit.
Dependencies are inferred from the claim text.