Methods and structure for on-chip clock jitter testing and analysis

An integrated circuit (IC) comprising:

• a Phase Locked Loop circuit (PLL) having an input coupled to receive a reference clock signal and adapted to generate and output an application clock signal;
• a sampling control circuit having an input coupled to receive the reference clock signal and having an input coupled to receive the application clock signal, the sampling control circuit adapted to acquire a plurality of samples of the application clock signal at each of a plurality of sample points, wherein the plurality of sample points span a period of time that comprises multiple clock periods of the application clock signal, wherein the plurality of samples are acquired based on the reference clock signal, wherein the plurality of sample points are offset in time relative to one another to sample different points of the multiple clock periods of the application clock signal, and wherein the sampling control circuit is further adapted to generate and output a count of the number of samples of the plurality of samples having a predetermined value at each of the plurality of sample points;
• and
• an analysis circuit having an input coupled to receive the count, the analysis circuit adapted to determine whether the count is within acceptable limits and further adapted to generate a pass/fail output signal indicating whether the count is within the acceptable limits,
• wherein the analysis circuit further comprises a acceptable limit comparator circuit having an input coupled to receive the count and having an input coupled to receive a predetermined acceptable limits range, the comparator circuit adapted to compare the count with the acceptable limits range and further adapted to generate the pass/fail output signal indicating whether the count is within the acceptable limits range.