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US 8,619,931 B1Granted
Multi-purpose phase-locked loop for low cost transceiver
AssigneeAltera Corporation
InventorsTien Duc Pham, Sergey Shumarayev, Tim Tri Hoang, Thungoc M. Tran, Vinh Van Ho, Leon Zheng
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Abstract
Integrated circuits having transceivers capable of high-speed (e.g., 1 Gbps) operation without dedicated phase-locked loop circuitry are provided. One such integrated circuit device may include one or more transceivers capable of transmitting and receiving serial signals of approximately 1 Gbps or greater, and a multi-purpose phase-locked loop capable of providing a multi-phase clock signal to the one or more transceivers.
Claims30
An integrated circuit device comprising:
- one or more transceivers capable of transmitting and receiving serial signals of approximately 1 Gbps or greater;
- and
- a multi-purpose phase-locked loop capable of providing a multi-phase clock signal to the one or more transceivers and to data utilization circuitry disposed on the integrated circuit device, wherein each of the transceivers comprises:
- a phase detector configured to receive the serial signals and a current clock signal, wherein the current clock signal is based at least in part on the multi-phase clock signal, and to output one or more recovered data signals that indicate data recovered from the serial signals and one or more alignment error signals that indicate whether the current clock signal is aligned with the serial signals;
- and
- a phase interpolator configured to receive a phase interpolator control signal and the multi-phase clock signal and to output the current clock signal, wherein the phase interpolator control signal is based at least in part on the one or more alignment error signals and wherein the current clock signal is approximately aligned with the serial input signals.
3 more elements
A method comprising:
- disposing, onto an integrated circuit device, a transceiver capable of being driven by a multi-phase clock signal;
- disposing, onto the integrated circuit device, receiver circuitry configured to:
- receive a serial signal and the multi-phase clock signal;
- generate a current clock signal based on the multi-phase clock signal;
- recover data from the serial signal by sampling the serial signal at various phases of the current clock signal;
- and
- generate a low frequency current clock signal by multiplying one phase of the current clock signal such that the resulting low frequency clock signal has approximately the same frequency as a reference clock signal;
- and
- disposing, onto the integrated a multi-purpose phase-locked loop circuit capable of generating the multi-phase clock signal, wherein the multi-purpose phase-locked loop circuit is configured to send the multi-phase clock signal to the transceiver and to data utilization circuitry.
6 more elements
An integrated circuit device comprising:
- a multi-purpose phase-locked loop configured to provide a multi-phase clock signal to a plurality of components of the integrated circuit, wherein the plurality of components comprises at least a transceiver configured to receive the multi-phase clock signal and data utilization circuitry configured to receive the multi-phase clock signal, wherein the transceiver comprises:
- a phase detector configured to receive a serial input signal and a current clock signal, wherein the current clock signal is based at least in part on the multi-phase clock signal, and to output one or more recovered data signals that indicate data recovered from the serial input signal and one or more alignment error signals that indicate whether the current clock signal is aligned with the serial input signal;
- and
- a phase interpolator configured to receive a phase interpolator control signal and the multi-phase clock signal and to output the current clock signal, wherein the phase interpolator control signal is based at least in part on the one or more alignment error signals and wherein the current clock signal is approximately aligned with the serial input signal.
1 more element
An integrated circuit device comprising:
- a multi-purpose phase-locked loop configured to generate a serial clock signal, a load enable signal, and a parallel data clock signal, wherein the frequency of the serial clock signal generated by the multi-purpose phase-locked loop is a multiple of the load enable signal;
- one or more transceivers configured to transmit and receive serial signals of approximately 1 Gbps or greater, wherein the one or more transceivers comprise:
- a serializer configured to load parallel data on the load enable signal and serialize the parallel data on the serial clock signal;
- and
- data utilization circuitry configured to provide the parallel data to the serializer on the parallel data clock signal.
2 more elements
An integrated circuit device comprising:
- a multi-purpose phase-locked loop circuit configured to generate a multi-phase clock signal based at least in part on a reference clock signal;
- one or more transceivers configured to receive a serial signal of approximately 1 Gbps or greater, wherein the one or more transceivers comprises:
- receiver circuitry configured to receive the serial signal and the multi-phase clock signal, to generate a current clock signal based on the multi-phase clock signal, to recover data from the serial signal by sampling the serial signal at various phases of the current clock signal, and to generate a low frequency current clock signal by multiplying one phase of the current clock signal such that the resulting low frequency clock signal has approximately the same frequency as the reference clock signal;
- a field programmable gate array (FPGA) fabric configured to receive the multi-phase clock signal;
- and
- clock error detecting circuitry configured to detect errors between the low frequency current clock signal and the reference clock signal.
3 more elements
Dependencies are inferred from the claim text.