Automatic gain control circuit and receiver circuit

An automatic gain control circuit comprising:

• a variable gain amplifier configured so that a gain is varied by a first control signal;
• a detector circuit to detect an intensity of an output signal of the variable gain amplifier;
• a comparator to compare the output signal of the detector circuit with a reference signal;
• an integrator to integrate a signal corresponding to an output signal of the comparator, and output an integration result to the variable gain amplifier as the first control signal;
• and
• a loop gain control unit, connected between the comparator and the integrator, and configured so that a loop gain is varied by a lock detection signal of a PLL (phase lock loop) circuit, the loop gain control unit including two coefficient multipliers to respectively multiply different filter coefficients to the output signal of the comparator, and a selector to select the filter coefficient to multiply to the output signal of the comparator based on the lock detection signal of the PLL circuit;
• and
• a level detection unit to detect a signal intensity of the output of the integrator, wherein the loop gain control unit includes:
• a plurality of first coefficient multipliers to multiply first filter coefficients, different from each other, to the output signal of the comparator;
• a first selector to select the first filter coefficient to multiply to the output signal of the comparator based on the detection result of the level detection unit;
• a plurality of second coefficient multipliers to multiply second filter coefficients, different from each other, to the output signal of the comparator;
• a second selector to select the second filter coefficient to multiply to the output signal of the comparator based on the detection result of the level detection unit;
• and
• a third selector to select the first filter coefficient selected by the first selector or the second filter coefficient selected by the second selector based on the lock detection signal of the PLL circuit.

A receiver circuit comprising:

• a low noise amplifier to amplify a reception signal;
• a first local oscillator to generate a first local oscillation signal based on an output of a first PLL (phase lock loop) circuit;
• a mixer to down-convert the reception signal by mixing the reception signal and the first local oscillation signal;
• a second local oscillator to generate a second local oscillation signal based on an output of a second PLL (phase lock loop) circuit;
• an AD (Analog to Digital) converter, to operate in synchronization with a clock signal generated from the second local oscillation signal, and convert an analog signal down-converted by the mixer to a digital signal;
• and
• an automatic gain control circuit to operate in synchronization with the clock signal generated from the second local oscillation signal, and control a gain of the digital signal output from the AD converter while controlling a loop gain of a feedback loop based on a lock detection signal of the first PLL circuit, the automatic gain control circuit including a variable gain amplifier configured so that a gain is varied by a first control signal, a detector circuit to detect an intensity of an output signal of the variable gain amplifier, a comparator to compare an output signal of the detector circuit with a reference signal, a loop filter to feed back an output signal of the comparator to the variable gain amplifier, an integrator, a level detection circuit to detect a signal intensity of an output of the integrator and a loop gain control unit, wherein the loop gain control unit includes:
• a plurality of first coefficient multipliers to multiply first filter coefficients, different from each other, to an output signal of the comparator;
• a first selector to select the first filter coefficient to multiply to the output signal of the comparator based on the detection result of the level detection unit;
• a second coefficient multiplier to multiply a second filter coefficient to the output signal of the comparator;
• and
• a second selector to select the first filter coefficient selected by the first selector or the second filter coefficient based on the lock detection signal of the PLL circuit.