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US 8,619,882 B2Granted
Data modulation circuit
AssigneeFujitsu Semiconductor Limited
InventorUichi Sekimoto
Life of this patent
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Abstract
A data modulation circuit has an adder adding an input signal, and an output signal of a memory device; and an output circuit part discriminating and quantizing the output signal of the adder by a predetermined threshold value. The memory device receives and holds the output signal of the adder and a predetermined signal, and supplies the held signals to the adder as an output signal of the memory device.
Claims8
A data modulation circuit, comprising:
- a memory circuit configured to output a first output signal;
- an adder configured to add a first input signal and the first output signal and to output a second output signal;
- a logic circuit configured to receive and logically process the second output signal and to output a third output signal;
- and
- an output circuit configured to discriminate and quantize the second output signal by a threshold value and to output a fourth output signal, wherein
- the memory circuit is configured to receive and hold the second output signal second input signal, and configured to combine the held signals and to output the combined signals to the adder as the first output signal, the second input signal including the third output signal;
- and
- the logic circuit is configured to receive and logically process the second output signal and the fourth output signal, and to output the second input signal to the memory circuit.
5 more elements
A data modulation circuit, comprising:
- a memory circuit configured to output a first output signal;
- an adder configured to add a first input signal and the first output signal and to output a second output signal;
- a logic circuit configured to receive and logically process the second output signal and to output a third output signal;
- and
- an output circuit configured to discriminate and quantize the second output signal by a threshold value and to output a fourth output signal, wherein
- the memory circuit is configured to receive and hold the second output signal second input signal, and configured to combine the held signals and to output the combined signals to the adder as the first output signal, the second input signal including the third output signal;
- the first input signal is an input digital signal of −2N to 2N−1, where N is a natural number;
- and
- the fourth output signal is an M-bit output digital signal, where M is a natural number less than N and the level of quantization is a 2M level.
6 more elements
A data modulation circuit, comprising:
- a memory circuit configured to output a first output signal;
- an adder configured to add a first input signal and the first output signal and to output a second output signal;
- a logic circuit configured to receive and logically process the second output signal and to output a third output signal;
- and
- an output circuit configured to discriminate and quantize the second output signal by a threshold value and to output a fourth output signal, wherein
- the memory circuit is configured to receive and hold the second output signal second input signal, and configured to combine the held signals and to output the combined signals to the adder as the first output signal, the second input signal including the third output signal;
- the first input signal is an input digital signal of 0 to 2N−1, where N is a natural number;
- and
- the fourth output signal is an M-bit output digital signal, where M is a natural number less than N and the level of the quantization is a 2M-1+1 level.
6 more elements
Dependencies are inferred from the claim text.